ARM ARM926EJ-S, Техническое справочное руководство

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Programmer’s Model
2-32 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D
2.3.11 TLB Lockdown Register c10
The TLB Lockdown Register controls where hardware page table walks place the TLB
entry, in the set associative region or the lockdown region of the TLB, and if in the
lockdown region, which entry is written. The lockdown region of the TLB contains
eight entries. See
TLB structure on page 3-31 for a description of the structure of the
TLB.
Writing the TLB Lockdown Register with the preserve bit (P bit) set to:
1 Means subsequent hardware page table walks place the TLB entry in the
lockdown region at the entry specified by the victim, in the range 0 to 7.
0 Means subsequent hardware page table walks place the TLB entry in the
set associative region of the TLB.
TLB entries in the lockdown region are preserved so that invalidate TLB operations
only invalidate the unpreserved entries in the TLB. That is, those in the set-associative
region. Invalidate TLB single entry operations invalidate any TLB entry corresponding
to the Modified Virtual Address given in Rd, regardless of their preserved state. That is,
if they are in the lockdown or set-associative regions of the TLB. See
TLB Operations
Register c8 on page 2-24 for a description of the TLB invalidate operations.
The instructions you can use to program the TLB Lockdown Register are shown in
Table 2-25.
Figure 2-14 shows the TLB Lockdown Register format.
Figure 2-14 TLB Lockdown Register format
The victim automatically increments after any table walk that results in an entry being
written into the lockdown part of the TLB.
Table 2-25 Programming the TLB Lockdown Register
Function Instruction
Read data TLB lockdown victim
MRC p15,0,<Rd>,c10,c0,0
Write data TLB lockdown victim
MCR p15,0,<Rd>,c10,c0,0
P SBZ
31 29 28 26 25 1 0
Victim SBZ/UNP