UG-1492
Rev. 0 | Page 4 of 22
EVALUATION BOARD HARDWARE
POWER SUPPLIES
The EVAL-AD5753SDZ requires power supply inputs for the
AV
DD1
, AV
DD2
, AV
SS
, and V
LOGIC
supplies. If there is only one
positive rail available, connect the AV
DD2
pin to the AV
DD1
pin
via the AVDD1-AVDD2-SHRT link. Select the V
LOGIC
supply from
the 3.3V_SDP evaluation board pin or the V
LDO
pin through the
VLOGIC_SOURCE link. See Table 1 for the default link positions
and see Table 2 for more linking options.
The EVAL-AD5753SDZ operates with a power supply range of
−33 V on AV
SS
to +33 V on AV
DD1
, with a maximum voltage of
60 V between the two rails. AV
DD2
requires a voltage between
5 V and 33 V. To bypass the positive dc-to-dc circuitry, connect
the V
DPC+
pin directly to AV
DD1
via the JP6 jumper. To bypass the
negative dc-to-dc circuitry, connect the V
DPC−
pin directly to the
AV
SS
pin via the JP5 jumper. The recommended supply voltages are
AV
DD2
= +5 V, AV
DD1
= +24 V, and AV
SS
= −24 V.
SERIAL COMMUNICATION
) handles communication to the
EVAL-AD5753SDZ via the PC. The
handles the serial port interface (SPI) communication, controls
the RESET pin and the LDAC pin, and monitors the FAULT pin
of the
Remove the appropriate links on P2 to disconnect the EVAL-
AD5753SDZ from the
) and drive the
digital signals from an external source. The S1 link and the JP11
link allow the user to tie RESET and LDAC to high or low levels.
The AD0 address pin and the AD1 address pin are used in
conjunction with the address bits within the SPI frame to
determine which
device is being addressed by the system
controller. Configure the AD0 pin and the AD1 pin through the
JP12 link and the JP14 link.
Table 1. EVAL-AD5753SDZ Link Option Functions
Link
Default Position
Function
AVDD1-AVDD2-SHRT
Not inserted
Connects AV
DD2
to AV
DD1
.
VLOGIC_SOURCE A
Position A selects 3.3 V from the
). Position B selects 3.3 V from the V
LDO
JP1 A
Position A powers the
reference (ADR-REF) from the V
LDO
pin. Position B powers the
ADR-REF from AV
DD2
. The maximum supply for the
is 15 V.
JP2
Inserted
Selects the ADR-REF pin as the input to the REFIN pin.
JP4
Not inserted
Selects the REFOUT pin as the input to the REFIN pin.
JP5
Not inserted
Shorts the V
DPC−
pin to the AV
SS
pin to bypass the negative dc-to-dc circuitry.
JP6
Not inserted
Shorts the V
DPC+
pin to the AV
DD1
pin to bypass the positive dc-to-dc circuitry.
JP7
Inserted
Shorts the ADC2 pin to the +V
SENSE
pin.
JP8 Inserted
Connects
the
VI
OUT
pin to the +V
SENSE
pin.
JP9
Not inserted
Connects the RETURN signal to the GND position on the EVAL-AD5753SDZ.
JP10
Inserted
Connects the −V
SENSE
pin to the RETURN signal.
JP11 A Position A connects the LDAC pin to the GND position. Position B connects the LDAC pin to the
V
LOGIC
pin.
JP12 A Position A connects the AD0 pin to the GND position. Position B connects the AD0 pin to the
V
LOGIC
pin.
JP13 B Position A connects the GPIO_0 pin to the GND position. Position B connects the GPIO_0 pin to
the V
LOGIC
pin.
JP14 A Position A connects the AD1 pin to the GND position. Position B connects the AD1 pin to the
V
LOGIC
pin.
JP15 B Position A connects the GPIO_2 pin to the GND position. Position B connects the GPIO_2 pin to
the V
LOGIC
pin.
JP16 B Position A connects the GPIO_1 pin to the GND position. Position B connects the GPIO_1 pin to
the V
LOGIC
pin.
JP17
Not inserted
Connects the AV
SS
pin to the GND position for the unipolar supply option (current output only).
P2 Inserted
Provides options to disconnect from the
) and to drive digital signals
from an external source. See Table 2 for the specific link options.
S1 2-3
Position 2-1 (on position to the right of off ) connects the RESET pin to the GND position.
Position 2-3 (on position to the left of off ) connects the RESET pin to the V
LOGIC
pin.
