Analog Devices ADSP-21369 EZ-KIT Lite, Руководство пользователя

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Switches
2-10 ADSP-21369 EZ-KIT Lite Evaluation System Manual
Boot Mode and Clock Ratio Select Switch (SW2)
The
SW2
switch sets the boot mode and clock multiplier ratio of the pro-
cessor. Table 2-3 shows how to set up the boot mode using
SW2
positions 1 and 2. By default, the EZ-KIT Lite boots in external port
mode from flash memory.
Table 2-4 shows how to set up the clock multiply ratio using
SW2
positions 3 and 4. By default, the processor increases the clock multiply
ratio by sixteen, setting the core clock to 393.216 MHz.
The core clock frequency can be increased or decreased via software by
writing to the
PMCTL
register. For more information on changing the core
clock frequency and other setup information, refer to the ADSP-2137x
SHARC Processor Hardware Reference (Includes ADSP-21367,
ADSP-21368, ADSP-21369, ADSP-21371, ADSP-21375)
.
Table 2-3. Boot Mode Configuration Switch (SW2)
BOOTCFG0 Pin (Position 1) BOOTCFG1 Pin (Position 2) Boot Mode
ON ON
SPI slave boot
ON OFF Parallel flash boot (default)
OFF ON
SPI master boot
OFF
OFF
Reserved
Table 2-4. Core Clock Rate Configuration
CLKCFG0 (Position 3) CLKCFG1 (Position 4) Core to CLKIN Ratio
ON ON
6:1
ON OFF 16:1 (default)
OFF ON
32:1
OFF
OFF
Reserved