System Architecture
2-2
ADSP-21369 EZ-KIT Lite Evaluation System Manual
System Architecture
This section describes the processor’s configuration on the EZ-KIT Lite
board (
Figure 2-1
).
The EZ-KIT Lite is designed to demonstrate the ADSP-21369 processor
capabilities. The processor core is powered at 1.3V, and the I/O is pow-
ered at 3.3V.
Figure 2-1. System Architecture Block Diagram
ADSP-21369
DSP
JTAG
Header
Power Regulation
PBs (4)
JTAG Port
A5V
+7.0V
Co
nnector
Expansion
Connectors
Type A
1M x 8
Flash
24.576 MHz
Oscillator
External
Port
3.3V
Stereo Out RCA
Jacks (4x2)
Stereo In RCA
Jacks (2x1)
DAI
1.3V
AD1835
CODEC
DPI
SPI FLASH
512k x 8
SRAM
SPDIF Out
Phono
FLAGs
0,1, and 3
2
2
Headphone
Jack
Reset PB
SPDIF In
Phono
4M x 32
SDRAM
LEDs
(8)
5
DPI
Conn
DAI
Conn
RS
232
Conn
ADM3202
ELVIS
Conn
1
2
USB
Co
nnector
Debug
Agent
Содержание ADSP-21369 EZ-KIT Lite
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