Analog Devices ADSP-21065L EZ-KIT Lite Скачать руководство пользователя

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TP1

HEADER 1X1 .100 TH

Male, single

Samtec: TSW-101-07-L-S

Voltage
Regulator

SO-8

10A, 3.3V

Analog Devices: ADP3310AR-3.3

U10

Silicon

Delay

Line

16-pin SOIC

Triple, 10-ns delay, +/- 2ns,
5.0V

Dallas Semi: DS1013S-10

U12

74LVCH162
45A

TSSOP-48

16-Bit Xcvr, w/ Bus Hold, 5V-
Tolerant, +/-24 mA, 1.5-4.1 ns,
3.3 V

IDT: IDT74LVCH16245APA
Phillips: 74LVCH16245A DGG

U13

Audio OpAmp 8-Pin SOIC

Dual - Single Supply (+4V to
+36V)

Analog Devices: SSM2135S

U14

74LCX574

TSSOP-20

Octal Edge Trigg D Flip-Flops
w/ 3-State out puts, 5V-
Tolerant, +/-24 mA, 1.5-8.5 ns,
3.3 V

Fairchild: 74LCX574MTC
Motorola: MC74LCX574DT

U15

SoundPort
Codec

48-pin TQFP

AC ‘97 Compliant, 5.0V

Analog Devices: AD1819A JST

U16

74LCX125

TSSOP-14

Quad bus buffers w/ 3-state
outputs, w/ Bus Hold, 5V-
Tolerant, +/-24 mA, 1.5-6.0 ns,
3.3 V

Fairchild: 74LCX125MTC
Motorola: MC74LCX125DT

U17

EPROM

32-pin DIP

EPROM 2Mb (256Kx8), 200ns,
3.3V

SGS: M27V201-200F6

Macronix: MX27L2000 DC-20

U18

SHARC DSP

208-pin PQFP

Processor, 60MHz, 3.3V

Analog Devices: ADSP-21065L KS-
240X

U19, U20

SDRAM

50-pin TSOP

SDRAM 16Mb (1Mx16),
83MHz, 3.3V

Micron: MT48LC1M16A1TG S-10
NEC: uPD4516161AG5-A10

Voltage
Regulator

SO-8

10A, 5V

Analog Devices: ADP3310AR-5

Voltage Monitor 8-pin SOIC

uProcessor Supervisor, 200ms,
3.3V

Analog Devices: ADM708TAR

www.BDTIC.com/ADI

Содержание ADSP-21065L EZ-KIT Lite

Страница 1: ...ADSP 21065L EZ KIT Lite Evaluation System Manual Part Number 82 000490 01 Revision 2 0 January 2003 www BDTIC com ADI...

Страница 2: ...piling the ADSP 21065L EZ KIT Lite operational software one copy may be made for back up purposes only No part of this document may be reproduced in any form without permission Trademark and Service M...

Страница 3: ...DARD OPERATION 17 3 2 1 I O Devices 17 3 2 2 POST Routines 20 3 2 3 Monitor Program Operation 22 3 2 4 AD1819 Transmissions 23 3 3 RUNNING YOUR OWN PROGRAMS 24 3 3 1 ADSP 21065L Memory Map 24 3 3 2 Us...

Страница 4: ...5 5 1 Boot Mode Selection Jumper 45 5 5 2 EPROM Size Selection Jumpers 46 5 5 3 Processor ID Jumpers 46 5 6 EPROM OPERATION 47 5 6 1 Designers Note 48 5 7 UART 48 5 7 1 Designers Note 48 5 8 EMAFE 49...

Страница 5: ...R 43 TABLE 5 2 EUROPEAN POWER SUPPLY SPECIFICATIONS 43 TABLE 5 3 BOOT MODE SELECTION 45 TABLE 5 4 EPROM SIZE SELECTION 46 TABLE 5 5 PROCESSOR SELECTION 46 TABLE 5 6 LINE IN SELECTION 47 TABLE 5 7 AD18...

Страница 6: ...PERS INSTALLED 45 FIGURE 5 4 EPROM ADDRESS 256K X 8 EXAMPLE 48 FIGURE 5 5 EMAFE WRITE CYCLE TIMING PARAMETER DEFINITIONS 50 FIGURE 5 6 EMAFE WRITE CYCLE TIMING DIAGRAM 51 FIGURE 5 7 EMAFE READ CYCLE T...

Страница 7: ...rform in circuit emulation through the processor s JTAG interface The board s features include Analog Devices ADSP 21065L DSP running at 60MHz Analog Devices AD1819A 16 bit SoundPort Codec RS 232 inte...

Страница 8: ...r re ea ac ch h o ou ur r C Cu us st to om me er r S Su up pp po or rt t g gr ro ou up p i in n t th he e f fo ol ll lo ow wi in ng g w wa ay ys s Email questions to dsptools support analog com Contac...

Страница 9: ...s and demonstration programs Chapter 5 Working With EZ KIT Lite Hardware Provides information on the Hardware aspects of the evaluation system Chapter 6 Expansion Connectors Provides information on EM...

Страница 10: ...ocuments VisualDSP Getting Started Guide VisualDSP User s Guide for the ADSP 21xxx Family DSPs Assembler Manual for the ADSP 21xxx Family DSPs C C Compiler Library Manual for the ADSP 21xxx Family DSP...

Страница 11: ...cumulate on the human body and equipment and can discharge without detection Permanent damage may occur on devices subjected to high energy discharges Proper ESD precautions are recommended to avoid p...

Страница 12: ...evaluation board running the debug monitor via the serial port no emulator or simulator support Additionally the linker will restrict the user to only 25 2 5k words of the ADSP 21065L s on chip progra...

Страница 13: ...ght up briefly The FLAG9 and power red LED remain on If the LEDs do not light up check the power connections To configure your board to take advantage of the audio capabilities of the demos use the fo...

Страница 14: ...Figure 2 1 Component Selection 14 www BDTIC com ADI...

Страница 15: ...Default Settings After you have installed the board and utility software your PC and EZ KIT Lite have the default settings shown in Table 2 2 You can change these settings through the Settings menu in...

Страница 16: ...the Debugger Help help file 16 www BDTIC com ADI...

Страница 17: ...819 codec s operation Running Your Own Programs Provides information about writing and running your own DSP executables that link with the monitor program to run on the EZ KIT Lite board 3 2 Standard...

Страница 18: ...ved for monitor 3 2 1 2 Interrupts Each of the three external interrupts IRQ0 2 of the ADSP 21065L are directly accessible through push button switches SW2 SW4 and SW6 on the EZ KIT Lite board IRQ0 1...

Страница 19: ...not communicate with the host if an interrupt higher than IRQ0 is used The board cannot communicate with the host if interrupt nesting is disabled If the user does not require the supplied monitor pro...

Страница 20: ...n reset disconnect power to the board for at least three seconds and then reconnect power The board automatically resets note that all the LED s light up briefly The user may also reset the board duri...

Страница 21: ...s that the ADSP 21065L is capable of writing to and reading from a register in the UART Three patterns are written to and then read from a register in the UART and tested All three patterns must be re...

Страница 22: ...ts of the monitor program Halt loop UART ISR Command Processing Kernel The monitor program idles in the Halt loop when it is not running user code While there you can read write memory read write regi...

Страница 23: ...instruction 3 2 4 AD1819 Transmissions After reset the AD1819 generates the clock used to transfer data across SPORT1 The ADSP 21065L initiates all transmissions with the AD1819 by sending a synchron...

Страница 24: ...The ADSP 21065L SHARC Technical Reference and ADSP 21065L SHARC User s Manual provides detailed information on programming the processor and the VisualDSP manuals provide information on code evaluati...

Страница 25: ...the interrupt handlers in libc dlb A correction will be posted to the Analog Devices FTP site Table 3 5 Memory Map Start Address End Address Content 0x0000 0000 0x0000 02FF Registers 0x0000 8000 0x000...

Страница 26: ...ocations internal RAM block 0 0x00009000 0x000097FF Kernel Code 48 bit internal block 0 0x0000C000 0x0000DFFF User space can be configured as 8192 x 32 or 2K x 48 4K x 32 or 4K x 48 2K x 32 0x01000000...

Страница 27: ...tion and example source that demon strates this second method contact Analog Devices DSP hotline or search our web site for the following document Interfacing The ADSP 21065L SHARC DSP to the AD1819a...

Страница 28: ...dard C runtime header 060_hdr asm This file also includes a jump to the EPROM codec interrupt handler at the SPORT1 Tx interrupt vector location Assembly use the demorth asm file as the interrupt vect...

Страница 29: ...4 With this structure set up by the monitor the user needs to only put data in the User Tx Buffer and then set Tx Request to 1 to send data to the codec 3 3 3 2 2 DSP Codec Receive Sequence 1 The rec...

Страница 30: ...0x030FFF0D User CODEC receive ready flag DM user_rx_ready When writing code the user needs to define variables so that they are linked in to these exact locations as was defined by the monitor kernel...

Страница 31: ...he linker to place these variables in the specified monitor kernel program locations for the codec in bank 3 This is done by including the following lines in the Linker Description File MEMORY seg_bnk...

Страница 32: ...0x8808 0x1C Record Gain RECORD_GAIN 0x0F0F 0x20 General Purpose GENERAL_PURPOSE 0x8000 0x78 Sample Rate 0 SAMPLE_RATE_GENERATE_0 0xBB80 0x7A Sample Rate 1 SAMPLE_RATE_GENERATE_1 0xBB80 3 3 5 EMAFE Pro...

Страница 33: ...ualDSP Debugger Guide Reference and the Debugger Tutorial for ADSP 2106x Family DSPs 4 2 Starting the VisualDSP Debugger After the VisualDSP software and license have been installed click the Windows...

Страница 34: ...window opens The code in the disassembly window is the EZ KIT Lite monitor program 4 3 Debugger Operation with the ADSP 21065L EZ KIT Lite The VisualDSP Debugger Guide Reference and the Debugger Tuto...

Страница 35: ...or the Window Refresh command Values may not be changed while the user program is running The current version of the VisualDSP Debugger does not let you view hardware stack information 4 3 3 Setting...

Страница 36: ...debug session without resetting the EZ KIT Lite board it is recommended to reset the board prior to loading a new program 4 4 Benchmarking Utilities An evaluation platform needs to report an accurate...

Страница 37: ...y location ecount_save These functions are completely self contained no saving or restoring of registers is necessary User must Run any program that uses this code from when the function count_start s...

Страница 38: ...to change how the DFT is performed This demo maps seg_dmda into SDRAM Therefore any added interrupts other then the codec s interrupt handler fail For more information see ADSP 21065L Memory Map 4 5 2...

Страница 39: ...formation see ADSP 21065L Memory Map 4 5 6 Tt dxe The Talk through demo samples data from the Line In of the AD1819 J8 on the board with JP1 and JP2 set appropriately at 48 kHz and then sends the data...

Страница 40: ...e board schematics are available as an insert at the end of this manual 5 2 System Architecture Figure 5 1 EZ KIT Lite System Block Diagram The Enhanced Modular Analog Front End EMAFE connector is acc...

Страница 41: ...bits of program storage that can be loaded by the ADSP 21065L when it is programmed to boot from EPROM Selection of the boot source is controlled by the BMS Boot Memory Select and BSEL EPROM Boot pins...

Страница 42: ...or user output that are available The FLAG 4 9 LEDs are controlled by the FLAG outputs of the DSP and are labeled according to the flag output that controls them See Flags section in Chapter 3 for mor...

Страница 43: ...oard Table 5 1 shows the power connector pinout If the user does not use the power supply provided with the EZ KIT Lite board replace it with one that has the connections shown in Table 5 1 Table 5 1...

Страница 44: ...bus speed and performance 5 4 5 EMAFE Interface Connector WARNING Using the EMAFE interface connector to connect to a MAFE board can damage the ADSP 21065L EZ KIT Lite the MAFE or both Enhanced Modula...

Страница 45: ...ch of the jumper selection blocks are described in the following sections 5 5 Jumpers 5 5 1 Boot Mode Selection Jumper The jumper JP6 controls the behavior of the ADSP 21065L processor when the system...

Страница 46: ...rs During typical operation of the EZ KIT Lite board there is only a single DSP in the system Jumpers JP7 and JP8 should be checked to guarantee that the board is configured as a single processor syst...

Страница 47: ...the AD1819 on the SPORT1 lines thereby preventing contention between the two devices When SPORT1 is not used by the EMAFE device or an EMAFE device is not installed JP3 should be connected to ground...

Страница 48: ...UART used is a 5V part therefore a 74LVTH245 is used to translate the data coming from the UART to the required 3 3V logic needed by the processor 5 7 1 Designers Note To access the UART correctly the...

Страница 49: ...21065L may be required for 5V non 3 3V compliant peripherals on the EMAFE board or from 5V peripherals on the EMAFE board to the 3 3v non 5V tolerant ADSP 21065L For information on EMAFE pins see EMAF...

Страница 50: ...Connect to the SDRAM s CLK pin SDCLK1 O S Z SDRAM SDCLK1 output pin Connect to the SDRAM s CLK pin SDWE I O Z SDRAM Write Enable pin Connect to SDRAM s WE or W buffer pin I Input O Output S Synchrono...

Страница 51: ...Figure 5 6 EMAFE Write Cycle Timing Diagram Figure 5 7 EMAFE Read Cycle Timing Parameter Definitions 51 www BDTIC com ADI...

Страница 52: ...Figure 5 8 EMAFE Read Cycle Timing Diagram 52 www BDTIC com ADI...

Страница 53: ...3 D0 D1 4 3 A0 A1 4 5 D2 D3 6 5 A2 A3 6 7 D4 D5 8 7 A4 A5 8 9 D6 D7 10 9 A6 A7 10 11 DGND D8 12 11 DGND A8 12 13 D9 D10 14 13 A9 A10 14 15 D11 D12 16 15 A11 A12 16 17 D13 D14 18 17 A13 A14 18 19 D15...

Страница 54: ...for evaluating present and future codec s and ADC s 18xx AD7xxx multimedia codec etc with the ADSP 21065L evaluation board Only the analog front end will be placed on a daughter board Each EMAFE daugh...

Страница 55: ...board 16 Data lines 8 Address lines 3 Parallel Bus Control lines 16 Synchronous Serial Port lines 1 Interrupt output 1 Flag input The EMAFE 96 pin connector also has the following power connections ro...

Страница 56: ...GND VDD1 2 NU VDD1 NU 3 VDD2 VDD2 NU 4 NU NU DGND 5 NU DGND NU 6 MD0 VDD1 MD1 7 MD2 NU MD3 8 MD4 NU MD5 9 DGND DGND DGND 10 MD6 NU MD7 11 MD8 NU MD9 12 MD10 NU MD11 13 VDD1 VDD1 VDD1 14 MD12 NU MD13 1...

Страница 57: ...P 21065L D26 A13 VDD1 Digital Power 5v A14 MD12 Parallel Data Bit 12 BUFFERED ADSP 21065L D28 A15 MD14 Parallel Data Bit 14 BUFFERED ADSP 21065L D30 A16 MFLAG Flag Input A17 DGND Digital Ground A18 NU...

Страница 58: ...igital Ground B16 NU Not Used B17 DGND Digital Ground B18 VDD2 Digital Power 3 3v B19 CLK_OUT CODEC Chain Clock B20 CHN_IN CODEC Chain Input B21 DGND Digital Ground B22 CS1 CODEC CS1 B23 DGND Digital...

Страница 59: ...ower 5v C14 MD13 Parallel Data Bit 13 BUFFERED ADSP 21065L D29 C15 MD15 Parallel Data Bit 15 BUFFERED ADSP 21065L D31 C16 MIRQ Interrupt Output Asserted Low C18 MA0 Parallel Address Bit 0 LATCHED ADSP...

Страница 60: ...tings and Demo menus The Settings menu provides access to the following commands Figure 7 1 Settings Menu Commands 7 2 1 Test Communications Tests the PC EZ KIT Lite communications Responses are Commu...

Страница 61: ...e baud rate and COM port should follow these instructions 1 Bring up the VisualDSP Configurator from the Windows Start menu Click Start Run then type Icecfg Figure 7 2 VisualDSP Configurator 61 www BD...

Страница 62: ...ick the Baud Rate and COM Port drop down list to change the settings Click OK to save the settings 7 2 2 Codec Sets several options for codec operation These commands are Update Updates and refreshes...

Страница 63: ...Figure 7 2 Sample Rate Dialog Source Choose Microphone or Line In Figure 7 3 Source Setting Gain Select Select a gain from 0 0 to 22 5 in 1 5 increments 63 www BDTIC com ADI...

Страница 64: ...inue with the demo Figure 7 4 FFT Demo Dialog Table 7 1 FFT Demo Dialog Description Dialog Field Description Source Select the source for the FFT the codec or a random number generator Domain Splits t...

Страница 65: ...ass Demo Controls Dialog The dialog fields for the Bandpass demo are as follows Input Source Select input from the AD1819 or noise from the DSP Filter Range Change the filter applied to the demo 65 ww...

Страница 66: ...e highest priority timer vector is used 7 The current version of the EZ KIT monitor does not let you view hardware stack information 8 Do not use the reset button while the debugger is open unless the...

Страница 67: ...tions performed are 1 Extends the EPROM read cycles board silicon revision 0 0 only The access cycles used by the ADSP 21065L when booting are too short for the EPROM therefore the CPLD deasserts the...

Страница 68: ...09 28 98 Changed functionality of Codec Reset 1usec low 21065L VHD VHDL code for the CPLD on the ASPL 21065L evaluation board Addresses A3 A2 A1 A0 UART 0 0 1 EMAFE_Address 0 0 0 0 EMAFE_Data 0 0 0 1...

Страница 69: ...st_bar 8 end interface architecture state_machine of interface is type StateType is IDLE CS1 CS2 WR1 WR2 WR3 WR4 WR_D1 ENDW1 ENDW2 ENDW3 ENDW4 CS3 CS4 CS5 CS6 RD1 RD2 RD3 RD4 ENDR1 signal present_stat...

Страница 70: ...d only if next_state CS2 addressed and rd wr else next_state IDLE Improper cycle end if when CS2 u_ack 0 Signal extended cycle u_ack_v 1 if wr 1 then next_state WR1 Write cycle else next_state CS3 Rea...

Страница 71: ...Cycle when CS5 u_ack 0 u_ack_v 1 next_state CS6 Continue Read Cycle when CS6 u_ack 0 u_ack_v 1 next_state RD1 Continue Read Cycle when RD1 u_ack 0 u_ack_v 1 next_state RD2 Continue Read Cycle when RD2...

Страница 72: ...E UART State u_rd_bar 1 UART State u_en_bar 1 UART State u_wr_bar 1 UART State present_wstate WAIT0 Wait State elsif rising_edge clk then present_state next_state UART State u_rd_bar uart_ctrl_d 2 UAR...

Страница 73: ...rol variable rd std_logic variable bms std_logic begin rd not rd_bar bms not bms_bar case present_wstate is when WAIT0 if bms 1 AND RD 1 then Check for EPROM RD w_ack 0 Yes Delay w_ack_v 1 next_wstate...

Страница 74: ...herwise key on rising edge if cdc_cnt 00000 then if counter hasn t started if addr 0100 AND cs_bar 0 then check if reset cdc_cnt cdc_cnt 1 Start counter codec_rst_bar 0 Reset codec else if not reset c...

Страница 75: ...APPENDIX B BILL OF MATERIALS 75 www BDTIC com ADI...

Страница 76: ...AT2A 6 18 C3 C9 C16 C17 C20 C47 C51 C57 C69 C97 C98 C99 C100 C111 C120 C126 C133 C138 10uF EIA3216 Tantalum 10 10 V Kemet T491A106K010AS 7 2 C39 C117 0 047uF SMT1206 Z5U 10 50 V Digikey PCC473BCT ND P...

Страница 77: ...SMT1206 0 025 Ohm DC 3A Murata BLM31P500S 21 9 FB4 FB5 FB6 FB7 FB8 FB9 FB10 FB11 FB12 EMI Filter 603 Bead Inductor 200 mA Murata BLM11A601SPB 22 2 HQ1 HQ2 SMT Heat Sink TO 263AB Conduction through Dra...

Страница 78: ...W Digi Key P5 1KACT ND 40 1 R5 1M Ohm SMT0805 Thick Film 5 1 10 W Digi Key P1 0MACT ND 41 2 R52 R53 33 Ohm x 8 SOP 16 Isolated 5 200 mW CTS 767 163 R33 Digikey 767 163 R33 ND 42 1 R54 10K x 15 SOP 16...

Страница 79: ...Fairchild 74LCX574MTC Motorola MC74LCX574DT 56 1 U15 SoundPort Codec 48 pin TQFP AC 97 Compliant 5 0V Analog Devices AD1819A JST 57 1 U16 74LCX125 TSSOP 14 Quad bus buffers w 3 state outputs w Bus Ho...

Страница 80: ...74F06 SOP 14 Open collector Hex inverter 3 5ns 5 0 V Phillips N74F06D 68 1 U9 32 Macro cell CPLD 44 Pin TQFP In Circuit Programmable 5 0V 75mA 12ns 5 0V 3 3V Cypress CY7C371i 83AC 69 1 X1 18 432 MHz S...

Страница 81: ...NOTE TRST is incorrectly documented in the schematic as active high It should be active low TRST Also REDY is incorrectly documented in the schematic as active low REDY It should be active high active...

Страница 82: ...9 79 FLAG10 78 FLAG11 76 RESET 157 CPA 65 CLKIN 30 XTAL2 31 GND35 196 DT0A 11 DT0B 12 TCLK0 8 TFS0 7 DR0A 5 DR0B 6 RCLK0 4 RFS0 2 DR1A 16 DR1B 17 RCLK1 15 RFS1 13 DT1A 22 DT1B 23 TCLK1 19 TFS1 18 PWM_...

Страница 83: ...A30 TFS1 A31 TXD1 A32 DGND B1 VDD1 B2 VDD2 B3 NC B4 DGND B5 VDD1 B6 NC B7 NC B8 DGND B9 NC B10 NC B11 NC B12 VDD1 B13 NC B14 DGND B15 NC B16 DGND B17 VDD2 B18 CLK_OUT B19 CHN_IN B20 DGND B21 CS1 B22 D...

Страница 84: ...12 A1 11 A2 10 A3 9 A4 8 A5 7 A6 6 A7 5 A8 27 A9 26 A10 23 A11 25 A12 4 A13 28 A14 29 A15 3 A16 2 A17 30 Q0 13 Q1 14 Q2 15 Q3 17 Q4 18 Q5 19 Q6 20 Q7 21 E 22 G 24 P 31 Vpp 1 Vss 16 Vcc 32 JP4 Jumper3...

Страница 85: ...S 1 Gate 3 Vout 5 GND 7 nc0 2 nc1 6 Q2 NDB6020P U2 ADP3310 5 0 Vin 4 EN 8 IS 1 Gate 3 Vout 5 GND 7 nc0 2 nc1 6 C5 100uF C3 10uF C17 10uF C16 10uF C6 0 1uF C19 0 1uF C18 0 1uF C2 1uF C15 1uF FB3 Ferrit...

Страница 86: ...SBTS D 0 31 A 0 23 PROM_CS MS0 MS1 CODEC_ON Mem Memory D 0 31 A 0 19 PROM_CS RD SDA10 MS3 RAS CAS SDWE DQM SDCKE SDCLK0 Codec Codec DT1A RFS1 DR1A RXCLK1 TXCLK1 CODEC_CS0 CODEC_CS1 CHAIN_IN CHAIN_CLK...

Страница 87: ...B9 5 9 4 8 3 7 2 6 1 X1 18 432MHz R6 1 5K R5 1M C55 27pF C56 47pF FB5 Ferrite Bead FB6 Ferrite Bead FB7 Ferrite Bead FB8 Ferrite Bead C46 0 1uF C43 0 1uF C40 0 1uF C41 0 1uF C45 0 1uF C54 220 pF C50 2...

Страница 88: ...Green R22 910 R21 910 R24 910 R19 910 D5 Green D4 Green R20 910 R23 910 D3 Green R31 10K U11D 74LCX14 9 8 U11E 74LCX14 11 10 14 7 U8C 74F06 5 6 14 7 R10 10K U4D 74LCX14 9 8 14 7 R11 100 Ohm R9 10K U1...

Страница 89: ...c 14 JP3 1 2 3 C101 0 1uF C104 0 1uF C113 1uF C98 10uF C114 270pF C99 10uF C102 0 1uF SJP3 Shunt C112 1uF X2 24 576MHz R46 100 Ohm C116 0 1uF C109 22pF C97 10uF C100 10uF C103 0 1uF C80 1nF FB9 Ferrit...

Страница 90: ...B board 12 Contents of package 11 CPLD Equations 66 Customer support 8 D data packets 22 using in CODEC transmissions 27 Debugger starting 32 Default Settings on the EZ LAB 15 Demo menu commands 63 De...

Страница 91: ...ers IMASK 17 MODE1 17 MODE2 17 Resetting the board 19 S SDRAM 48 SDRAM data mask See DQM SDRAM interface data transfer rate 48 features 48 pin definitions See SDRAM interface pin definitions SDRAM mem...

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