when ENDW1 => u_ack <= '0';
u_ack_v <= '1';
next_state <= ENDW2; -- Continue Write Cycle
when ENDW2 => u_ack <= '0';
u_ack_v <= '1';
next_state <= ENDW3; -- Continue Write Cycle
when ENDW3 => u_ack <= '0';
u_ack_v <= '1';
next_state <= ENDW4; -- Continue Write Cycle
when ENDW4 => u_ack <= '1';
u_ack_v <= '1';
next_state <= IDLE; -- End Write Cycle
when CS3 => u_ack <= '0';
u_ack_v <= '1';
next_state <= CS4; -- Continue Read Cycle
when CS4 => u_ack <= '0';
u_ack_v <= '1';
next_state <= CS5; -- Continue Read Cycle
when CS5 => u_ack <= '0';
u_ack_v <= '1';
next_state <= CS6; -- Continue Read Cycle
when CS6 => u_ack <= '0';
u_ack_v <= '1';
next_state <= RD1; -- Continue Read Cycle
when RD1 => u_ack <= '0';
u_ack_v <= '1';
next_state <= RD2; -- Continue Read Cycle
when RD2 => u_ack <= '0';
u_ack_v <= '1';
next_state <= RD3; -- Continue Read Cycle
when RD3 => u_ack <= '0';
u_ack_v <= '1';
next_state <= RD4; -- Continue Read Cycle
when RD4 => u_ack <= '1';
u_ack_v <= '1';
next_state <= ENDR1; -- Continue Read Cycle
when ENDR1 => u_ack <= '1';
u_ack_v <= '1';
next_state <= IDLE; -- End Read Cycle
end
case;
end process uart_state;
with next_state select --
uart_ctrl_d <= "111" when IDLE,
"101" when CS1,
"101" when CS2,
"100" when WR1,
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