ADM1026
PRELIMINARY TECHNICAL DATA
– 2 6 –
REV. PrL
PRELIMINAR
Y
TECHNICAL
DA
TA
input furthest from NTESTOUT (RESETMAIN). This
should give the characteristic output pattern shown in
Figure 22, with NTESTOUT toggling each time an input
is taken high.
G P IO 16
G P IO 15
G P IO 14
G P IO 13
G P IO 12
G P IO 11
G P IO 10
G P IO 9
G P IO 8
F AN0
F AN1
F AN2
F AN3
F AN4
F AN5
F AN6
F AN7
S CL
S DA
CI
IN T
P W M
R ESET ST B Y
R ESET M A IN
NT E S TO UT
Figure 22. NAND Tree Test Taking Inputs High In Turn
1. Start with all inputs high and take them low in turn,
starting with the input furthest from NTEST_OUT
(RESETMAIN) and working down the tree to the input
nearest to NTEST_OUT (GPIO16/THERM). This
should give a similar output pattern to Figure 23.
Notes:
1. When generating test waveforms, a typical propagation
delay of 500 ns through the NAND tree should be al-
lowed for.
2. If any of the inputs shown in Figure 21 are unused,
they should not be connected direct to ground, but via
a resistor such as 10k
⍀
. This will allow the ATE (Au-
tomatic Test Equipment) to drive every input high so
that the NAND tree test can be properly carried out.
R ESET M A IN
R ESET ST B Y
P W M
IN T
CI
S DA
S CL
F AN7
F AN6
F AN5
F AN4
F AN3
F AN2
F AN1
F AN0
G P IO 8
G P IO 9
G P IO 10
G P IO 11
G P IO 12
G P IO 13
G P IO 14
G P IO 15
G P IO 16
NT E S TO UT
Figure 23. NAND Tree Test taking Inputs Low In Turn
In the event of an input being non-functional(stuck high
or low) or two inputs shorted together, the output pattern
will be different. Some examples are given in Figures 24
to 26.
G P IO 16
G P IO 15
G P IO 14
G P IO 13
G P IO 12
G P IO 11
G P IO 10
G P IO 9
G P IO 8
F AN 0
F AN 1
NT E S T O U T
Figure 24. NAND Tree Test With GPIO11 Stuck Low
Figure 24 shows the effect of one input being stuck low.
The output pattern is normal until the stuck input is
reached. Because that input is permanently low, neither it
nor any inputs further up the tree can have any effect on
the output.
