PRELIMINARY TECHNICAL DATA
ADM1026
– 2 3 –
REV. PrL
PRELIMINAR
Y
TECHNICAL
DA
TA
1 = O UT
O F L IM IT
HI
G
H
A
N
D
LO
W
LI
MI
T
CO
M
PA
R
A
TO
R
S
IN T
E NA BL E
IN T
C LE A R
IN T
L AT CH
RE S E T
IN
O UT
M AS K
RE G IS TE R 1
M AS K D AT A FR O M
S M BUS (S AM E BIT
NA M E S A N D O RD E R
AS S T AT U S B IT S )
S T AT US
BIT
M AS K
BIT
M AS K G AT IN G
⫻
⫻
⫻
⫻
8
IN T T em p
V BA T
AIN8
T HE RM
AF C
RE S E RV E D
CI
G P IO 16
S
T
AT
US
R
E
G
IST
ER
4
0
1
2
3
4
5
6
7
ST
A
T
U
S
R
E
G
IST
ER
1
0
1
2
3
4
5
6
7
E xt1 T em p
E xt 2 T em p
3.3V S T BY
3.3V M AIN
+5V
V
C C P
+12V
-12V
F AN 0
F AN 1
F AN 2
F AN 3
F AN 4
F AN 5
F AN 6
F AN 7
F RO M F A N S P E E D
V AL UE A N D
L IM IT R EG IS T E RS
S
T
AT
US
R
E
G
IST
ER
3
0
1
2
3
4
5
6
7
HI
G
H
L
IMI
T
CO
M
P
AR
AT
O
R
DA
T
A
DE
M
UL
TI
PL
EX
ER
1 = O UT
O F L I M IT
V A L U E
HIG H L I M IT
M AS K R E G IS T E R 5
M AS K R E G IS T E R 6
S T AT US R E G IS T E R 6
G P IO 0 TO GP IO 7
G P IO 8 TO G P IO15
S T AT US R E G IS T E R 5
M AS KIN G D AT A
F RO M S M BU S
M AS KIN G D AT A
F RO M S M BU S
ST
A
T
U
S
R
E
G
IST
ER
2
0
1
2
3
4
5
6
7
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
HIG H L I M IT
L O W L I M IT
V A L U E
F RO M A NA LO G /TE M P .
V AL UE A ND LIM IT
RE G IS TE R S
DA
T
A
DE
M
U
L
T
IP
L
E
X
E
R
M AS K
RE G IS TE R 2
M AS K
RE G IS TE R 4
M AS K
RE G IS TE R 3
M AS K G AT IN G
⫻
⫻
⫻
⫻
8
S T AT US
BIT
M AS K
BIT
M AS K D AT A FR O M
S M BUS (S AM E BIT
NA M E S A N D O RD E R
AS S T AT U S B IT S )
M AS K D AT A FR O M
S M BUS (S AM E BIT
NA M E S A N D O RD E R
AS S T AT U S B IT S )
S T AT US
BIT
M AS K
BIT
M AS K G AT IN G
⫻
⫻
⫻
⫻
8
S T AT US
BIT
M AS K
BIT
M AS K G AT IN G
⫻
⫻
⫻
⫻
8
S T AT US
BIT
M AS K
BIT
M AS K G AT IN G
⫻
⫻
⫻
⫻
8
M AS K G AT IN G
⫻
⫻
⫻
⫻
8
S T AT US
BIT
M AS K
BIT
M AS K D AT A FR O M
S M BUS (S AM E BIT
NA M E S A N D O RD E R
AS S T AT U S B IT S )
L AT CH
RE S E T
IN
O UT
CI
G P IO 16
Figure 15. ADM1026 Interrupt Structure
