ADAV4622
Rev. B | Page 20 of 2
8
SCL
Serial clock for the I
2
C control port. SCL features a glitch
elimination filter that removes spurious pulses that are less
than 50 ns wide.
MUTE
Mute input request. This active-low input pin controls the
muting of the output ports (both analog and digital) from the
ADAV4622. When low, it asserts mute on the outputs that are
enabled in the audio flow.
RESET
Active-low reset signal. After RESET goes high, all the circuit
blocks are powered down. The blocks can be individually
powered up with software. When the part is powered up, it
takes approximately 3072 internal clocks to initialize the
internal circuitry. The internal system clock is equal to MCLKI
until the PLL is powered and enabled, after which the internal
system clock becomes 2560 × f
S
(122.88 MHz). Once the PLL
is powered up and enabled after reset, it takes approximately
3 ms to lock. When the audio processor is enabled, it takes
approximately 32,768 internal system clocks to initialize and
load the default flow to the audio processor memory. The audio
processor is not available during this time.
AUXIN1L, AUXIN2L, AUXIN1R, AND AUXIN2R
Analog inputs to the on-chip ADCs.
AUXOUT1L, AUXOUT2L, AUXOUT3L, AUXOUT4L,
AUXOUT1R, AUXOUT2R, AUXOUT3R, AND
AUXOUT4R
Auxiliary DAC analog outputs. These pins can be programmed
to supply the outputs of the internal audio processing for line
out or record use.
HPOUT1L, HPOUT2L, HPOUT1R, AND HPOUT2R
Analog outputs from the headphone amplifiers.
PLL_LF
PLL loop filter connection. A 100 nF capacitor and a 2 kΩ
resistor in parallel with a 1 nF capacitor tied to AVDD are
required for the PLL loop filter to operate correctly.
VREF
Voltage reference for DACs and ADCs. This pin is driven by an
internal 1.5 V reference voltage.
FILTA AND FILTD
Decoupling nodes for the ADC and DAC. Decoupling
capacitors should be connected between these nodes and
AGND, typically 47 μF/0.1 μF and 10 μF/0.1 μF, respectively.
PWM1A, PWM1B, PWM2A, PWM2B, PWM3A,
PWM3B, PWM4A, AND PWM4B
Differential pulse-width modulation outputs are suitable for
driving Class-D amplifiers.
PWM_READY
This pin is set high when PWM is enabled and stable.
AVDD
Analog power supply pins. These pins should be connected to
3.3 V. Each pin should be decoupled with 10 μF and 0.1 μF
capacitors to AGND, as close to the pin as possible.
DVDD
Digital power supply. This pin is connected to a 1.8 V digital
supply. Connecting 10 μF and 0.1 μF decoupling capacitors to
DGND, as close to the pin as possible, is strongly recommended
for optimal performance.
ODVDD
Digital interface power supply pin. This pin should be
connected to a 3.3 V digital supply. The pin should be
decoupled with 10 μF and 0.1 μF capacitors to DGND, as
close to the pin as possible.
DGND
Digital ground.
AGND
Analog ground.
ODGND
Ground for the digital interface power supply.
SIF_REFP, SIF_REFCM, AND SIF_REFN
Decoupling nodes for the SIF block.
SIF_IN1 AND SIF_IN2
Analog inputs for the SIF block.
SIF_PGA_REF
PGA reference output. This pin should be decoupled to AGND
with 10 μF and 0.1 μF capacitors.
ISET
ADC current setting resistor.
