ADAV4622
Rev. B | Page 10 of
28
TIMING DIAGRAMS
MCLKI
RESET
t
MP
= 1/
f
MCLKI
t
RESET
07
06
8-
0
04
Figure 2. Master Clock and Reset Timing
0706
8-
036
t
JIT
t
CH
t
CL
t
CK
DVDD
GND
Figure 3. Master Clock Output Timing
LRCLK1
BCLK1
SDINx
SDO0
t
SLS
t
SLH
t
SDS
t
SDH
t
SDD
07
06
8-
0
0
2
Figure 4. Serial Port Slave Mode Timing
LRCLK1
BCLK1
SDINx
SDO0
t
MLD
t
MDS
t
MDH
t
MDD
07
06
8-
0
0
3
Figure 5. Serial Port Master Mode Timing
07
06
8
-03
3
ODVDD
100µA
I
OL
100µA
I
OH
TO OUTPUT
PIN
50pF
Figure 6. Load Circuit for Digital Output Timing Specifications
