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AD1849K

REV. 0

–13–

Control Byte 4, Test Register

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

0

0

0

0

0

0

ENL

ADL

39

38

37

36

35

34

33

32

ENL

Enable loopback testing:

0

Disabled

1

Enabled

ADL

Loopback mode:

0

Digital loopback from Data/Control receive to Data/Control transmit (D-D)

1

Analog loopback from DACs to ADCs (D-A-D)

Control Byte 5, Parallel Port Register

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

PIO1

PIO0

0

0

0

0

0

0

31

30

29

28

27

26

25

24

PIO1:0 Parallel I/O bits for system signaling. PIO bits do not affect Codec operation.

Control Byte 6, Reserved Register

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

0

0

0

0

0

0

0

0

23

22

21

20

19

18

17

16

Reserved bits should be written as 0.

Control Byte 7, Revision Register

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

0

0

1

0

REVID3

REVID2

REVID1

REVID0

15

14

13

12

11

10

9

8

REVID3:0

Silicon revision identification. Reads greater than or equal to 0010 (i.e., 0010, 0011, etc.) for the AD1849K.

Control Byte 8, Reserved Register

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

0

0

0

0

0

0

0

0

7

6

5

4

3

2

1

0

Reserved bits should be written as 0.

Содержание AD1849K

Страница 1: ...are available over a single bidirectional serial interface that also sup ports 16 bit digital input to the DACs and control information The AD1849K can accept and generate 8 bit law or A law compande...

Страница 2: ...Line 1 External Load Capacitance 100 pF Line 0 1 ANALOG INPUT Min Typ Max Units Input Voltage RMS Values Assume Sine Wave Input Line and Mic with 0 dB Gain 0 94 0 99 1 04 V rms 2 66 2 80 2 94 V p p Mi...

Страница 3: ...Interchannel Gain Mismatch Line and Mic 0 3 dB Difference of Gain Errors DIGITAL TO ANALOG CONVERTERS Min Typ Max Units Resolution 16 Bits DAC Dynamic Range 60 dB Input THD N Referenced 80 86 dB to Fu...

Страница 4: ...Scale Output Voltage Line 0 1 0 707 V rms OLB 1 1 85 2 0 2 1 V p p Full Scale Output Voltage Line 0 1 0 V rms OLB 0 2 8 V p p Full Scale Output Voltage Line 1 4 0 V p p OLB 0 Full Scale Output Voltage...

Страница 5: ...o Valid tZV 15 ns Output Valid to Hi Z tVZ 20 ns Power Up RESET LO Time 50 ms Operating RESET LO Time 100 ns POWER SUPPLY Min Typ Max Units Power Supply Voltage Range 4 75 5 25 V Digital and Analog Po...

Страница 6: ...atic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the AD1849K features propri...

Страница 7: ...l Line Input MINL 17 11 I Left Channel Microphone Input 20 dB from Line Level if MB 0 or Line Level if MB 1 MINR 15 9 I Right Channel Microphone Input 20 dB from Line Level if MB 0 or Line Level if MB...

Страница 8: ...riod is 10 7 milliseconds at a 48 kHz sampling rate and 64 milliseconds at an 8 kHz sampling rate Time out ms 512 Sampling Rate kHz Monitor Mix A monitor mix is supported that digitally mixes a portio...

Страница 9: ...d to prevent undesired outputs Monitor mix will be automatically disabled by the Codec During the autocalibration sequence the serial data output from the ADCs is meaningless and the ADI bit is assert...

Страница 10: ...provided to generate a wide range of sample rates The oscillators for these crystals are on the AD1849K as is a multiplexer for selecting between them They can be overdriven with external clocks by th...

Страница 11: ...ntrol Byte 1 Status Register Data 7 Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 0 0 0 1 MB OLB DCB 0 AC 63 62 61 60 59 58 57 56 MB Mic bypass 0 Mic inputs applied to 20 dB fixed gain block 1 Mic in...

Страница 12: ...4 43 42 41 40 ITS Immediate three state 0 FSYNC SDTX and SCLK three state within 3 SCLK cycles after D C goes LO 1 FSYNC SDTX and SCLK three state immediately after D C goes LO MCK2 0 Clock source sel...

Страница 13: ...PIO1 0 Parallel I O bits for system signaling PIO bits do not affect Codec operation Control Byte 6 Reserved Register Data 7 Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 0 0 0 0 0 0 0 0 0 23 22 21...

Страница 14: ...4 R13 R12 R11 R10 R9 R8 47 46 45 44 43 42 41 40 In 16 bit linear PCM mode this byte contains the upper eight bits of the right audio data sample In the 8 bit companded and linear modes this byte conta...

Страница 15: ...ther ADC channel is driven beyond the specified input range It is sticky i e it remains set until explicitly cleared by writing a 0 to OVR A 1 written to OVR is ignored allowing OVR to remain 0 until...

Страница 16: ...transition from Control Mode to Data Mode those control register values that are not changeable in Control Mode get reset to the defaults above except PIO The control registers that can be changed in...

Страница 17: ...e and in many systems the lowest jitter clocks available will be those generated by the Codec s internal oscillators Conversely SCLK in many systems will be the noisiest source The master SCLK clock s...

Страница 18: ...e host for operation Subsequent transitions to Control Mode after initialization are expected to be relatively infrequent Control information that is likely to change frequently e g gain levels is tra...

Страница 19: ...provides a convenient mechanism for transferring signaling information between the serial data and control streams and the external pair of bidirectional pins also named PIO1 and PIO0 The states of th...

Страница 20: ...Handshaking Protocol The D C pin can make transitions completely asynchronously to internal Codec operation This fact necessitates a handshaking protocol to ensure a smooth transition between serial...

Страница 21: ...andshake the AD1849K and the CS4215 DCB protocols are equivalent Control Mode to Data Mode Transition and Autocalibration The AD1849K will enter Data Mode when the asynchronous D C signal goes HI The...

Страница 22: ...OR AD820 0 33 F 0 33 F Figure 12 AD1849K Phantom Powered Microphone Input Circuit Figure 13 shows ac coupled line outputs The resistors are used to center the output signals around analog ground If d...

Страница 23: ...201 746 0333 Note that using the exact data sheet frequencies is not required and that external clock sources can be used to overdrive the AD1849K s internal oscillators See the description of the MCK...

Страница 24: ...ort Codec to four of Analog Devices Fixed Point DS Ps The ADSP 2111 ADSP 2101 and ADSP 2115 use their multichannel serial port for the data interface and flag outputs for D C The ADSP 2105 has a singl...

Страница 25: ...single pole active filter requiring a dual op amp Though overkill for the AD1849K this input circuit will work with the AD1849K as well The AD1849K was designed to require no external low pass filter...

Страница 26: ...MPLE FREQUENCY FS Figure 25 AD1849K Analog to Digital Frequency Response Transition Band Full Scale Line Level Inputs 0 dB Gain 10 120 1 0 90 110 0 1 100 0 0 60 80 70 50 30 20 0 10 40 0 8 0 9 0 7 0 6...

Страница 27: ...TROL REGISTERS 11 Control Mode Control Registers 11 Data Mode Data and Control Registers 14 Control Register Defaults 16 SERIAL INTERFACE 17 Frames and Words 17 Clocks and the Serial Interface 17 Timi...

Страница 28: ...0 013 0 33 0 056 1 42 0 042 1 07 0 025 0 63 0 015 0 38 0 180 4 57 0 165 4 19 0 63 16 00 0 59 14 99 0 110 2 79 0 085 2 16 0 040 1 01 0 025 0 64 0 050 1 27 BSC 0 020 0 50 R PIN 1 IDENTIFIER BOTTOM VIEW...

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