AD1849K
REV. 0
–12–
Control Byte 2, Data Format Register
Data 7
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 0
0
0
DFR2
DFR1
DFR0
ST
DF1
DF0
55
54
53
52
51
50
49
48
DFR2:0
Data conversion frequency (F
S
) select tin kHz):
DFR
Divide Factor
XTAL1 (24.576 MHz)
XTAL2 (16.9344 MHz)
0
3072
8
5.5125
1
1536
16
11.025
2
896
27.42857
18.9
3
768
32
22.05
4
448
N/A
37.8
5
384
N/A
44.1
6
512
48
33.075
7
2560
9.6
6.615
Note that the AD1849K’s internal oscillators can be overdriven by external clock sources at the crystal input pins. If an
external clock source is used, it should be applied to the crystal input pin (CIN1 or CIN2), and the crystal output pin
(COUT1 or COUT2) should be left unconnected. The external clock source need not be at the recommended crystal
frequencies, and it will be divided down by the selected Divide Factor.
ST
Global stereo mode. Both converters are placed in the same mode.
0
Mono mode. The left analog input appears at both ADC outputs. The left digital input appears at both DAC outputs.
1
Stereo mode
DF1:0
Codec data format selection:
0
16-bit twos-complement PCM linear
1
8-bit
µ
-law companded
2
8-bit A-law companded
3
8-bit unsigned PCM linear
Control Byte 3, Serial Port Control Register
Data 7
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 0
ITS
MCK2
MCK1
MCK0
FSEL1
FSEL0
MS
TXDIS
47
46
45
44
43
42
41
40
ITS
Immediate three-state:
0
FSYNC, SDTX and SCLK three-state within 3 SCLK cycles after D/
C
goes LO
1
FSYNC, SDTX and SCLK three-state immediately after D/
C
goes LO
MCK2:0
Clock source select for Codec internal operation:
0
Serial bit clock (SCLK) is the master clock at 256
×
F
S
1
24.576 MHz crystal (XTAL1) is the clock source
2
16.9344 MHz crystal (XTAL2) is the clock source
3
External clock (CLKIN) is the clock source at 256
×
F
S
4
External clock (CLKIN) is the clock source, divided by the factor selected by DFR2:0
(External clock must be stable and valid within 2000 periods after it is selected.)
FSEL1:0
Frame size select:
0
64 bits per frame
1
128 bits per frame
2
256 bits per frame
3
Reserved
Note that FSEL is overridden in Data Mode when SCLK is the clock source (MCK = “0”). When SCLK is
providing the 256
×
F
S
clock for internal Codec operation, 256 bits per frame is effectively selected, regardless of
FSEL’s contents.
MS
Master/slave mode for the serial interface:
0
Receive serial clock (SCLK) and TSIN from an external device (“slave mode”)
1
Transmit serial clock (SCLK) and frame sync (FSYNC) to external devices (“master mode”)
Note that MS is overridden when SCLK is the clock source (MCK = “0”). When SCLK is providing the clock for
internal Codec operation, slave mode is effectively selected, regardless of the contents of MS.
TXDIS
Transmitter disable:
0
Enable serial output
1
Three-state serial data output (high impedance)
Note that Control Mode overrides TXDIS. In Control Mode, the serial output is always enabled.
