AMPTRON 3IBAT, Руководство пользователя

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3IBAT User’s Manual
EDO DRAM Speed Selection
The DRAM timing is controlled by the DRAM Timing Registers. The timings
programmed into this register are dependent on the system design. Slower
rates may be required in certain system designs to support loose layouts or
slower memory.
50ns DRAM Timing Type.
60ns DRAM Timing Type.
EDO CASx# MA Wait State
You could select the timing control type of EDO DRAM CAS MA (memory
address bus).
The choice: 1, 2
EDO RASx# Wait State
You could select the timing control type of EDO DRAM RAS MA (memory
address bus).
The Choice: 1, 2.
SDRAM RAS-to-CAS Delay
You can select RAS to CAS Delay time in HCLKs of 2/2 or 3/3. The system
board designer should set the values in this field, depending on the DRAM
installed. Do not change the values in this field unless you change specifi-
cations of the installed DRAM or the installed CPU..
The Choice: 2, 3.
SDRAM RAS Precharge Time
Defines the length of time for Row Address Strobe is allowed to precharge.
The Choice: 2, 3.
SDRAM CAS latency Time
You can select CAS latency time in HCLKs of 2/2 or 3/3. The system board
designer should set the values in this field, depending on the DRAM installed.
Do not change the values in this field unless you change specifications of
the installed DRAM or the installed CPU.
The Choice: 2, 3.
DRAM Data Integrity Mode
Select Parity or ECC (error-correcting code), according to the type of in-
stalled DRAM.
The Choice: Non-ECC, ECC.