AMIMON AMN12310 WHDI Скачать руководство пользователя страница 22

Interfaces 

Version 0.5 

 

 

AMIMON Confidential 

 

22 

3.4.1.3  MAC uC Write Operation 

Figure  8  demonstrates  a  write  transaction  which  sends  2  data  bytes  and  which  ends  with  the  master  stop  bit. 
Each write transaction sends one or more data bytes to the MAC, beginning at an explicit 2 bytes long address. 
Multiple data bytes may be written as the MAC stores the received register data until the master sends a stop bit. 
The MAC updates the register value upon a successful termination of a write transaction. 

I

6

write

I

5

...

Two-Wire Slave address

ack

A

15

A

8

A

14

...

register address

ack

A

7

A

0

A

6

...

register address

ack

D7

D0

D6

...

register data0

ack

D

7

D

0

D

6

...

register data1

ack

STOP

START

 

Figure 8: Two-Wire MAC Write Commands 

3.4.1.4  MAC uC Read Operation 

This  operation  reads  from a  specific  2-  byte  address.  The  read  transaction  is  divided  into  two  parts. In  the  first 
part, the Two-Wire master sends a write command to the slave containing only the required start address.  (The 
address is always 2 bytes long.) In the second part, multiple bytes may be read from consecutive addresses. The 
MAC  puts  the  appropriate  data  on  the  Two-Wire  bus  and  the  internal  address  is  automatically  incremented.  A 
stop bit is sent by the master only when the entire transaction has been completed. 

I

6

write

I

5

...

Two-Wire Slave address

ack

register address

ack

register address

START

ack

A

15

A

8

A

14

...

A

7

A

0

A

6

...

I

6

read

I

5

...

Two-Wire slave address

ack

START

Data Byte 0

register data

ack

Data Byte 1

register data

ack

STOP

 

Figure 9: Two-Wire Read Command 

3.4.1.5  WHDI Application/MAC Protocol 

The  WHDI  programmer’s  reference  defines  the  MAC  registers  data  structure.  Each  register  has  an  associated 
group id and index offset address. 

The group id and  the index offset  are  each  1  byte  long. Together they  define a register address  that  is 2  bytes 
long. 

Each register has an attributed length (in byte units). All registers within the same group have the same length. 

A Two-Wire transaction to a specific register includes 2 bytes of register address and the register data bytes. The 
register is written in one transaction. If the transaction terminates ahead of time or is too long, the MAC issues an 
error  interrupt  and  does  not  store  the  received  values.  The  register  is  read  in  one  transaction,  as  described  in 
section 

 

3.4.1.4. If the read transaction finishes ahead of time, the MAC issues an error interrupt. 

3.4.2  Interrupts 

There  is  one  interrupt  connected  to  the  WHDI  connector.  The  interrupt  source  is  the  AMN2210  MAC  uC.  For 
details about the interrupt, please refer to the programmer's user guide. . The interrupt active polarity is set in SW 
or by configuration resistors on board – see 

 

3.4.3. 

Содержание AMN12310 WHDI

Страница 1: ...Version 0 5 AMIMON Confidential 1 AMN12310 WHDITM Receiver Module Datasheet Version 0 5...

Страница 2: ...or process in which AMIMON products or services are used Information published by AMIMON regarding third party products or services does not constitute a license from AMIMON to use such products or s...

Страница 3: ...g Conditions and Electrical Characteristics modified AMN11310 Block Diagram modified Unhide Certification Compliance Power requirements Mini MAC changed to MAC WHDI Module Configuration Connector Sche...

Страница 4: ...ver 12 2 2 STM32F MAC Controller 12 2 3 AMN3210 WHDITM 5GHz Transceiver 13 2 4 Power Amplifier PA 13 2 5 Board Connector WHDI TM Connector 13 2 6 Clocks 13 2 6 1 40MHz Crystal Oscillator 13 2 6 2 40Mh...

Страница 5: ...s 26 4 2 Connector Schematics 27 4 3 Pin List 28 Chapter 5 30 Electrical Specifications 30 5 1 Operating Conditions and Electrical Characteristics 30 Chapter 6 32 Design Guidelines 32 6 1 Digital Layo...

Страница 6: ...t Mechanism 24 Figure 12 WHDI Connector 27 Figure 13 Mechanical Dimensions Top View 36 Figure 14 Mechanical Dimensions Bottom View 37 Figure 15 RF Shield Frame 38 Figure 16 RF Shield Cover 38 List of...

Страница 7: ...List of Tables Version 0 5 AMIMON Confidential 7 Table 13 Electrical Characteristics over Recommended Range of Supply Voltage and Operating Conditions 30 Table 14 Digital Layout Recommendation 32...

Страница 8: ...ransmits uncompressed video and audio streams wirelessly and thus simplifies and eliminates system issues such as lip sync large buffers and other burdens like retransmissions or error propagation 1 1...

Страница 9: ...by Amimon for compliance could void the user s authority to operate the equipment This equipment has been tested and found to comply with the limits for a Class B digital device pursuant to part 15 of...

Страница 10: ...Version 0 5 AMIMON Confidential 10 Caution The module should be positioned so that personnel in the area for prolonged periods may safely remain at least 20 cm 8 in in an uncontrolled environment fro...

Страница 11: ...ess input channels and one slow rate output wireless channel which generates an upstream channel for data content transmissions The outputs from the VDU are digital uncompressed video digital audio an...

Страница 12: ...ard by the MAC uC WHDI TM Baseband Receiver AMN2210 Downlink De modulation Uplink modulation Video Interface Audio Interface Control ADC DAC ADC ADC ADC ADC Video Sink Audio Sink MiniMAC MicroControll...

Страница 13: ...e components 2 4 Power Amplifier PA In order to extend the operating range for the AMN12310 upstream the RF transmitter uses a power amplifier The power amplifier has an output power detector for TPC...

Страница 14: ...for re generating the video clock The PLL receives a lower speed clock generally limited to 10 MHz which is generated inside the AMN2210 according to the video parameters The PLL multiplies the clock...

Страница 15: ...nfigurations are done on the transmitter end The video output data is uncompressed digital video up to 3 10 bits in width The video interface provides a direct connection to the inputs of a display de...

Страница 16: ...Cr 5 BLUE Cb RED Cr GREEN Y 6 BLUE Cb GREEN Y RED Cr The AMN123100 allows any of the output video channels options The first option is the default from power up In order to change the video channel m...

Страница 17: ...riate clock and data If the transmitter end was configured to SPDIF audio interface then the audio is output on the receiver side through the SPDIF The same is true for the I 2 S interface No constrai...

Страница 18: ...efault the serial data is valid on the leading LOW to HIGH edge of the clock signal but it can also be configured to be valid on the edge HIGH to LOW of the clock signal The WS is also valid by defaul...

Страница 19: ...falling edge 25 ns 3 3 1 3 Timing Diagram TSCKCYC TDCKPDR TSCKDUTY SCK SD WS 50 TSCKCYC TDCKPDF TSCKDUTY SCK SD WS 50 EDGE 1 EDGE 0 Figure 6 I2 S Output Timings 3 3 1 4 MCLK Specifications In addition...

Страница 20: ...TDCKPDF Propagation delay after MCK falling edge 25 ns TJITTER CYC CYC Cycle to cycle jitter 5 ns The minimum frequency is obtained by using the minimum audio sampling frequency of 32 KHz and the mini...

Страница 21: ...AC Two Wire Slave SDA SCL Figure 7 Two Wire Application MAC Connection On top of the Two Wire low level operation described in sections 3 4 1 3 and 3 4 1 4 the WHDI Application and the MAC microcontro...

Страница 22: ...ntire transaction has been completed I6 write I5 Two Wire Slave address ack register address ack register address START ack A15 A8 A14 A7 A0 A6 I6 read I5 Two Wire slave address ack START Data Byte 0...

Страница 23: ...MN2110 and to the STM32F uC as described in Figure 11 Assertion of the STM32F reset switches the clock of uC to the internal oscillator until the Albatross does not assert an INIT_DONE interrupt Asser...

Страница 24: ...W reset until valid clock is generated 40 MHz clock is valid few us after power up 300 ns TST RST Time from assertion of the HW reset until the STM32F completes the internal initialization Power is st...

Страница 25: ...Interfaces Version 0 5 AMIMON Confidential 25...

Страница 26: ...S LRCLK I2 S Word Select Left right clock which defines also the sampling rate Audio Out 1 MCLK I 2 S master clock coherent to WS according to specified ratio Audio Out Rate is adjustable on RX side 1...

Страница 27: ...WHDI Connector Pins Version 0 5 AMIMON Confidential 27 4 2 Connector Schematics Figure 12 WHDI Connector...

Страница 28: ...I_D16 52 WHDI_D17 13 3 3V 14 3 3V 53 WHDI_D14 54 WHDI_D15 15 GND 16 GND 55 GND 56 WHDI_D13 17 GND 18 GND 57 WHDI_DCLK 58 WHDI_D11 19 GND 20 GND 59 NC 60 WHDI_D9 21 GND 22 GND 61 WHDI_D12 62 WHDI_D7 23...

Страница 29: ...WHDI Connector Pins Version 0 5 AMIMON Confidential 29...

Страница 30: ...D Module supply voltage 3 15 3 3 3 45 V VSS Supply ground 0 V VIH High level input voltage 0 7 DVDD V VIL Low level input voltage 0 3 DVDD V VOH High level output voltage DVDD MIN IOH MAX 0 8 DVDD V V...

Страница 31: ...Electrical Specifications Version 0 5 AMIMON Confidential 31...

Страница 32: ...nit Control Impedance Notes 1 Component side CS 1 1 5 oz 1 Trace Width 14mil Separation 12 mil to ground plane 50 OHM COPLANAR 2 Trace Width 5 5 mil Separation between differential lines 5 5 mil diffe...

Страница 33: ...ts pins Series resistors on input lines are unnecessary The series resistors should be placed on the interface board 6 1 4 Power and Ground Use a solid ground plan Ground plans separation is unnecessa...

Страница 34: ...S_TDO TP10 TH GND TP37 SMD GND TP11 SMD GND TP38 SMD 3 3V TP12 SMD GND TP39 SMD 3 3V TP13 TH GND TP40 SMD HW_ID_0 TP14 SMD GND TP41 SMD HW_ID_1 TP15 SMD 3 3V J1 SMD RF UFL CON TP16 SMD GND J2 SMD RF U...

Страница 35: ...Design Guidelines Version 0 5 AMIMON Confidential 35...

Страница 36: ...Mechanical Dimensions Version 0 5 AMIMON Confidential 36 Chapter 7 Mechanical Dimensions The following shows the mechanical dimensions for the AMN12310 Figure 13 Mechanical Dimensions Top View...

Страница 37: ...Mechanical Dimensions Version 0 5 AMIMON Confidential 37 Figure 14 Mechanical Dimensions Bottom View...

Страница 38: ...Mechanical Dimensions Version 0 5 AMIMON Confidential 38 7 1 RF Shield frame and cover Figure 15 RF Shield Frame Figure 16 RF Shield Cover...

Страница 39: ...Mechanical Dimensions Version 0 5 AMIMON Confidential 39...

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