AMD ATI CTM, Техническое справочное руководство

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Conditional Operation Unit 5
© 2006 Advanced Micro Devices, Inc. ATI CTM Guide v. 1.01
If conditional program execution is enabled, however, program execution on a given pair may be skipped. Prior to
scheduling an index pair to a processor, the PE sends it to the Conditional Operation Unit (CO), along with its
conditional value. The CO performs a conditional test (as described in Section 2.1.3) based on the index pair and
conditional value, and returns its result to the PE. If the test fails, the index pair is skipped; otherwise a processor in
the array is scheduled to run the current program on the pair. The conditional value is set with the
set_cond_val
command (see page 10). Conditional program execution is enabled by setting the conditional location to the PE with
the
set_cond_loc command (see page 22).
The PE maintains counters that may be useful in analyzing CTM's performance. These are total clocks since last reset
and total clocks during which at least one processor was active since last reset. The
init_perf_counters (see page 12
for performance counter commands) sets up the counters for initial use. Start_perf_counters resets the counters and
starts them counting; Stop_perf_counters stops the counters. The counters may be read into an array in GPU-
addressable system memory using read_perf_counters. Read_perf_counters takes one parameter, which gives the
GPU address of the first element of the array. Total clocks is written in the first element; the second element is clocks
active.
2.1.3 Conditional Operation Unit
The Conditional Operation Unit (CO) performs a conditional test for clients within CTM. Clients include the PE (for
conditional program execution) and the DPP (for conditional program output). The CO evaluates a condition based
on an index pair (i, j) and a conditional value v, which are both sent to the CO by a requesting client.
The CO test is one of three possible cases: the test always passes, the test always fails, or the test is a comparison
between the conditional value v from a client to a value b read from a conditional output buffer residing in memory:
result = v op b, where op is one of <, <=, =, >=, or >
The conditional output buffer value b is obtained by the CO issuing a read request to the Memory Controller Unit with
index pair (i, j) and the conditional output buffer identifier (see page 7). The CO test is set with the
set_cond_test
command (see page 21).
In addition, if the conditional test passes, the CO will write the client conditional value v to the conditional output
buffer by issuing a write request to the MC with index pair (i, j) and the conditional output identifier.
2.1.4 Memory Controller Unit
The Memory Controller Unit (MC) translates addresses and satisfies requests to read and write memory for clients
within CTM. Clients include the PE (for command buffers), the CO (for the conditional buffer), and the DPP (for
program instructions, floating-point, integer, and boolean constants, inputs, and outputs). The MC can read or write
two kinds of memory: private memory that is accessible only by the MC (local memory), and memory that is
accessible both by the MC and a host processor (remote or system memory).
An MC memory address is a 32-bit unsigned integer. The MC distinguishes between local and remote memory by
maintaining distinct address ranges for each, within its 32-bit address range. The address mapping is system-
dependent and is described in the ATI CTM Device Interface.
The MC computes the memory address as a function of an index pair, (x, y), the number of elements in each row of
data (pitch), a base address offset (offset), a tiling format (linear or tiled plus an optional 2x2 superfine tiling on single-
channel input data reads), and the bytes per element (bpe) derived from the data format (format). The amount of data
read from or written to memory at this address is given by the bytes per element.
The address translation for the different data formats is summarized in the following two tables. If the tiling format
of the memory is linear, the address is provided in Table 1. If, on the other hand, the memory is tiled, the address is
given in Table 2.