© 2006 Advanced Micro Devices, Inc.
ATI CTM Guide v. 1.01
Chapter 2
Specifications
CTM is designed to expose the parallel array of floating-point processors found in ATI graphics hardware. It is
controlled with a few commands to set parameters, invalidate and flush caches, and start the processors in the
processing array. These commands reside in memory (see ATI CTM Device Interface for further information). This
chapter specifies how CTM reads these commands and its behavior upon processing each.
A block diagram of CTM is presented in Figure 2-1. In addition to the ATI Data Parallel Processor Array (DPP), CTM
comprises three major components: the Processor Execution Unit (PE), the Conditional Operation Unit (CO), and the
Memory Contoller Unit (MC).
Figure 2-1: CTM Block Diagram
The PE reads commands sequentially from a specified area of memory. Besides redirecting commands to other units
within CTM, the PE distributes processing work to the DPP. The computation on an individual processor is subject
to a condition returned by the CO. Program output results are written to memory, also based upon a condition returned
by the CO. Memory for instructions, constants, program inputs, program outputs, and a buffer used by the CO is
accessed through the MC. In addition to satisfying read and write requests, the MC computes memory address offsets,
based on a description of the format of the requested data in memory.
2.1
CTM Units
The following sections describe the CTM units in detail.
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