ATI CTM Guide v. 1.01
© 2006 Advanced Micro Devices, Inc.
30 ALU Instructions
3.3.6
Writemasks
There are a number of writemasks for each instruction:
Flow control instructions only have one predicate select, using the RGB_PRED_SEL and RGB_PRED_INV fields.
ALU/Output instructions can use different predicate selects for the RGB (vector) computation and the alpha (scalar)
computation. For texture instructions, the RGB results from the texture unit will be influenced by RGB_PRED_SEL/
RGB_PRED_INV, and the alpha result from the texture unit will be influenced by the ALPHA_PRED_SEL/
ALPHA_PRED_INV fields.
3.3.7
Destination
The destination address refers to a temporary register. The loop variable (aL) may optionally be added to the address
before writing. The predicate select in RGB_PRED_SEL, RGB_PRED_INV, ALPHA_PRED_SEL, and
ALPHA_PRED_INV will be applied when writing to the destination.
3.3.8
Output
With OUTPUT instructions, the TARGET field indicates where the result of the instruction should be written. When
in cached write mode (the default mode), the following options are available:
• RNDR_TGT_A - Write to render target A register
• RNDR_TGT_B - Write to render target B register
• RNDR_TGT_C - Write to render target C register
Writemask
Size
Description
RGB_WMASK
3 bits
Write R,G,B to register destination.
ALPHA_WMASK
1 bit
Write A to register destination.
RGB_OMASK
3 bits
Write R,G,B to output or to predicate bits.
ALPHA_OMASK
1 bit
Write A to output or to predicate bits.
W_OMASK
1 bit
Write A to W output.
WRITE_INACTIVE
1 bit
If set, ignores flow control processor mask when writing. Affects ALU and
texture instructions. If in doubt, this bit should be cleared.
RGB_PRED_SEL
3 bits
Sets one of six modes that specify which of the 4 predicate bit(s) to AND with
the RGB writemask (and output mask when applicable). One of:
• NONE - no predication
• RGBA - normal predication
• RRRR - replicate R predicate bit
• GGGG - replicate G predicate bit
• BBBB - replicate B predicate bit
• AAAA - replicate A predicate bit
RGB_PRED_INV
1 bit
Inverts selected RGB predicate bit(s). Should be zero if RGB_PRED_SEL is
set to NONE.
ALPHA_PRED_SEL
3 bits
Like RGB_PRED_SEL, but used to control predication for the alpha unit's
write mask.
ALPHA_PRED_INV
1 bit
Inverts selected alpha unit predicate bit. Should be zero if ALPHA_PRED_SEL
is set to NONE.
IGNORE_UNCOVERED
1 bit
If set, excludes uncovered processors (outside triangle or killed via TEXKILL)
from TEX lookups and flow control decisions. Affects texture and flow
control instructions. If in doubt, this bit should be cleared.
ALU_WMASK
1 bit
If set, update the ALU result. Similar to the predicate write mask.
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