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5-166

Bus Interface

AMD-K5 Processor Technical Reference Manual

18524C/0—Nov1996

HOLD-Initiated
Inquire Hit to Shared
or Exclusive Line

Figure 5-14 shows HOLD asserted in the same clock that the
processor begins a read cycle. The processor completes the
read (which is a burst read) and asserts HLDA two clocks after
the last BRDY of the in-progress cycle. It also floats all output
and bidirectional signals used for memory or I/O accesses at
the same time it asserts HLDA.

In the next clock after sampling HLDA asserted, system logic
initiates an inquire cycle by asserting EADS and INV and driv-
ing an inquire address on A31–A5. The inquire cycle hits a
shared or exclusive line (HIT asserted and HITM negated two
clocks after EADS) and the processor invalidates the cache
line (not visible on the bus). System logic negates HOLD in the
clock after EADS, and two clocks later (one clock after HIT
and HITM transition) the processor negates HLDA and contin-
ues with its other bus cycles.

If EADS is asserted in the same clock that HOLD is negated,
the processor recognizes this as a valid inquire cycle and han-
dles it correctly. However, if EADS is asserted in the clock fol-
lowing the negation of HOLD, the processor does not recognize
this as a valid inquire cycle.

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Содержание AMD-K5

Страница 1: ...AMD K5 Processor Technical Reference Manual TM...

Страница 2: ...ness of the contents of this publication or the information contained herein and reserves the right to make changes at any time without notice AMD disclaims responsibility for any consequences resulti...

Страница 3: ...Retire 2 12 2 3 Cache Organization and Management 2 13 2 3 1 Instruction Cache 2 14 2 3 2 Data Cache 2 15 2 3 3 Cache Tags 2 16 2 3 4 Cache Line Fills 2 17 2 3 5 Cache Coherency 2 18 2 3 6 Snooping 2...

Страница 4: ...ecific Registers MSRs 3 25 3 2 1 Machine Check Address Register MCAR 3 25 3 2 2 Machine Check Type Register MCTR 3 26 3 2 3 Time Stamp Counter TSC 3 27 3 2 4 Array Access Register AAR 3 27 3 2 5 Hardw...

Страница 5: ...5 45 5 2 14 BUSCHK Bus Check 5 46 5 2 15 CACHE Cacheable Access 5 49 5 2 16 CLK Bus Clock 5 52 5 2 17 D C Data or Code 5 53 5 2 18 D63 D0 Data Bus 5 55 5 2 19 DP7 DP0 Data Parity 5 57 5 2 20 EADS Exte...

Страница 6: ...Cycle Definitions 5 136 5 3 2 Addressing 5 137 5 3 3 Alignment 5 137 5 3 4 Bus Speed and Typical DRAM Timing 5 139 5 3 5 Bus Cycle Priorities 5 139 5 4 Bus Cycle Timing 5 140 5 4 1 Timing Diagrams 5 1...

Страница 7: ...Real Mode 5 195 6 System Design 6 1 6 1 Memory 6 1 6 1 1 Memory Map 6 2 6 1 2 Memory Decoder Aliasing of Boot ROM Space 6 4 6 1 3 Cacheable and Noncacheable Address Spaces 6 4 6 1 4 SMM Memory Space...

Страница 8: ...Design Support and Peripheral Products 6 43 7 Test and Debug 7 1 7 1 Hardware Configuration Register HWCR 7 3 7 2 Built In Self Test BIST 7 5 7 2 1 Normal BIST 7 5 7 2 2 Test Access Port TAP BIST 7 6...

Страница 9: ...after the Cacheability of the Line is Established A 8 Comments A 9 A 3 3 Snoop Before Write Hit to ICACHE Appears on Bus A 9 A 3 4 Invalidations during a FLUSH WBINVD A 9 A 3 5 Cache Line Ownership A...

Страница 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...

Страница 11: ...2 Figure 5 8 Burst Writeback Due To Cache Line Replacement 5 155 Figure 5 9 AHOLD Initiated Inquire Miss 5 158 Figure 5 10 AHOLD Initiated Inquire Hit to Shared or Exclusive Line 5 159 Figure 5 11 AHO...

Страница 12: ...Protected Mode to Real Mode 5 196 Figure 6 1 Typical Desktop System BIOS Memory Map 6 3 Figure 6 2 Default SMM Memory Map 6 7 Figure 6 3 BOFF Example 6 16 Figure 6 4 AHOLD and BOFF Example 6 18 Figur...

Страница 13: ...Interrupt Behavior and Interrupt Table Access 3 23 Table 3 7 Machine Check Type Register MCTR Fields 3 27 Table 3 8 CPU Clock Frequencies Bus Frequencies and P Rating Strings 3 29 Table 4 1 Integer In...

Страница 14: ...able 5 22 Interrupt Acknowledge Operation Definition 5 175 Table 5 23 Encodings For Special Bus Cycles 5 180 Table 5 24 Branch Trace Message Special Bus Cycle Fields 5 187 Table 6 1 Initial State of R...

Страница 15: ...A full description of the x86 programming environment is beyond the scope of this manual Instead the software sections describe differences from the 486 processor s programming environment A list of c...

Страница 16: ...as INTR are shown without an overbar Dual state signals such as R S and WB WT have two states of assertion and therefore the term asserted has no meaning such dual state signals are driven High or Low...

Страница 17: ...bits without writing their state to any storage resource Cache Invalidation The INVD instruction invalidates the contents of the in struction and data caches without writing modified data back to mem...

Страница 18: ...warm or soft reset can refer either to the assertion of RESET after power up or to the assertion of INIT System Logic Any logic outside the processor including a core logic chipset another bus master...

Страница 19: ...oint Arithmetic ANSI IEEE Std 754 1985 Institute of Electrical and Electronics Engineers IEEE Standard for Radix Indepen dent Floating Point Arithmetic ANSI IEEE Std 854 1987 Institute of Electrical a...

Страница 20: ...86 Advanced Programming New York Van Nostrand Reinhold 1993 Slater Michael Microprocessor Based Design Englewood Cliffs Prentice Hall 1989 Stallings William Operating Systems New York Macmillan 1992 V...

Страница 21: ...pment and support of the popular Am386 and Am486 processors has given it a broad foundation of experi ence in the x86 architecture The AMD K5 processor s binary compatibility with DOS and Windows comp...

Страница 22: ...igh Performance Execution Six execution units two ALUs two load store one branch one floating point Up to four instructions issued per processor clock Out of order issue and completion Speculative exe...

Страница 23: ...stamp counter TSC Machine Specific Registers MSRs 4 Mbyte page size Global pages held in TLB during flushes Low Power Static 3 3 V design System Management Mode SMM with I O trapping Low power halt an...

Страница 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...

Страница 25: ...em ory management Figure 2 1 shows the major logic blocks that make up the inter nal architecture The blocks are organized in the figure by stages of the processor s execution pipeline which are liste...

Страница 26: ...Reservation Station Port 41 bits Address Data 32 8 Ports 4 Ports 5 Ports 2 Ports Load Store Prefetch Predecode Branch Prediction Instruction Cache Linear Tags Byte Queue Fast Path M Code Fast Path M...

Страница 27: ...the fetch logic adds the code segment base to the effective address and places the resulting linear address in the prefetch program counter which then increments as a linear address along a sequentia...

Страница 28: ...ghput performance The sixth stage Retire may occur at a variable number of clocks after the Result stage but the Retire stage does not affect throughput performance when the processor operates in a no...

Страница 29: ...xecute a Dispatch ROPs to execution units Calculate operand linear address1 b Execute Arbitrate for result bus Access operands in data cache1 Check protection and segment limit1 Result Forward to exec...

Страница 30: ...in the cache line to be executed whether or not the branch will be taken and the cache index of the branch target called the successor index When the caches are invalidated all branch predictions are...

Страница 31: ...ocessor uses a combination of hardware and microcode to convert x86 instructions into ROPs The hardware consists of four parallel fastpath converters that translate the most commonly used x86 instruct...

Страница 32: ...h execution unit has its own FIFO reservation station with two or four entries ROPs are dispatched to reservation sta tions in program order One ROP can be dispatched to a single reservation station i...

Страница 33: ...uses Execution results are sent to the reorder buffer ROB over five 41 bit result buses Tags forwarded to the execution units represent results to watch for on one of the result buses No special compi...

Страница 34: ...store per clock Each unit holds copies of segment descriptor fields so that it can calculate logical and linear addresses and check protection variables and segment limits Data loaded by one instructi...

Страница 35: ...am counter associated with each instruction resolves ROP level dependencies stores speculative results provides the most recent copy of a register to execution units recovers from mispredicted branche...

Страница 36: ...OB facilitates precise exception handling any external interrupts that were latched or are cur rently held asserted are recognized and the instruction pointer is updated For instructions that store an...

Страница 37: ...me on the AMD K5 processor is a performance advan tage The enabling and operating modes for the caches are software controlled by the CD and NW bits of CR0 When disabled both caches are locked They ar...

Страница 38: ...s within a sin gle 32 byte line or they can be split into two 8 byte accesses across two contiguous lines Split line fetches can provide instructions from sequential lines in a single clock This keeps...

Страница 39: ...ite two parallel accesses per clock if not to the same bank MESI cache coherency protocol maintained by physical tags Requested word first line fill protocol Round robin replacement policy Read write...

Страница 40: ...two clocks to the one clock linear tag access Accesses to the instruction cache physical tags add three clocks to the one clock linear tag access Thus physical tag accesses take a total of three clock...

Страница 41: ...f an invalid line cannot be found in one of the four ways for the index a line is pseudo randomly selected for replacement from one of the four ways Then the processor fills the line by driving a four...

Страница 42: ...te related states The instruction cache implements coherency with only a valid bit which in effect works like a shared invalid subset of the MESI protocol The coherency state bits are stored in the ph...

Страница 43: ...exclusive exclusive writeback modified modified writeback Cache Write Write Miss Linear invalid single write invalid invalid Write Hit Linear shared cache update and single write shared or exclusive4...

Страница 44: ...hysical shared or exclu sive invalid invalid modified burst write write back FLUSH Signal Physical shared or exclu sive invalid invalid modified burst write write back WBINVD Instruction Physical shar...

Страница 45: ...the conditions under which snooping occurs in the AMD K5 processor and the resources that are snooped All such snooping is done in the processor s physical tags in paral lel with the processor s own a...

Страница 46: ...ructions if INV is negated the line remains invalid or shared but if INV is asserted the line is invalidated For data if INV is negated valid lines remain in or transition to the shared state a modifi...

Страница 47: ...data cache write is performed The AMD K5 processor like the 486 processor but unlike the Pentium processor requires a jump near or far after a self modifying write to clear the prefetch cache However...

Страница 48: ...cess to the bus and in which certain types of cacheable read cycles on the bus are promoted ahead of certain types of write cycles when the EWBE signal is asserted The AMD K5 processor has no such rea...

Страница 49: ...e data cache and it would become a writethrough going externally to main memory at the same time that it updates the data cache Replacement and Invalidation Writeback Buffer The processor has a 1 entr...

Страница 50: ...r for map ping 4 Mbyte pages Mappings to 4 Kbyte and 4 Mbyte pages can be intermixed in a given page directory the base of which is pointed to by the contents of control register 3 CR3 During memory a...

Страница 51: ...e store buffer 2 4 2 Read Write Reordering The processor reorders certain types of cacheable read cycles on the bus ahead of certain types of write cycles Specifically any read that hits in the instru...

Страница 52: ...he TLB is accessed and it alone can issue a page related excep tion TLB invalidations flushes are done in the standard ways a MOV to CR3 which loads a new page table directory or the INVLPG instructio...

Страница 53: ...E Accessed or Dirty bit a hit during the physical tag snoop causes the cache line to be invalidated Details on software configuration for 4 Mbyte paging are given in Section 3 1 2 on page 3 5 The glob...

Страница 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...

Страница 55: ...ut modification Because the AMD K5 processor takes a significantly different approach to implementing the x86 architecture some subtle differences from the Pentium processor may be visible to sys tem...

Страница 56: ...hapter 7 3 1 Control Register 4 CR4 Extensions Control register 4 contains bits that enable or specify many of the extensions to the 486 architecture The majority of the bits in CR4 are reserved The d...

Страница 57: ...sabled See Section 3 1 2 on page 3 5 for details 3 DE Debugging Extensions Enables I O breakpoints in the DR7 DR0 registers 1 enabled 0 disabled See Section 7 5 on page 7 16 for details 2 TSD Time Sta...

Страница 58: ...ed the processor does the following when either type of bus error occurs Latches the physical address of the failed cycle in its 64 bit machine check address register MCAR Latches the cycle definition...

Страница 59: ...y associative 4 Mbyte TLB which is separate from the 128 entry 4 Kbyte TLB From a given page directory the processor can access both 4 Kbyte pages and 4 Mbyte pages and the page sizes can be intermixe...

Страница 60: ...Size PS bit in the page directory entry to 1 3 Write the physical base addresses of 4 Mbyte pages in bits 31 22 of page directory entries Bits 21 12 of these entries must be cleared to 0 or the proces...

Страница 61: ...Bits 11 0 of the linear address select a byte in a 4 Kbyte page whose physical base address is specified by the page table entry 4 Mbyte Paging Figure 3 3 Bits 31 22 of the linear address select an e...

Страница 62: ...or does not change it 0 not written 1 written For 4 Mbyte pages the processor sets this bit to 1 during a write to the page that is mapped by this page directory entry 0 not written 1 written 5 A Acce...

Страница 63: ...aded For example entries may reference operating system code and data pages that are always required The processor operates faster if these entries are retained across task switches and procedure call...

Страница 64: ...re 3 5 Page Table Entry PTE Available to Software AVL 11 9 Global G 8 Page Size 0 PS 7 Dirty D 6 Accessed A 5 Page Cache Disable PCD 4 Page Writethrough PWT 3 User Supervisor U S 2 Write Read W R 1 Pr...

Страница 65: ...rite to the page that is mapped by this page table entry 0 not written 1 written 5 A Accessed The processor sets this bit to 1 during a read or write to any page that is mapped by this page table entr...

Страница 66: ...lable on the AMD K5 proces sor the operating system controls Virtual 8086 mode access to the IF flag by trapping instructions that can read or write this flag These instructions include STI CLI PUSHF...

Страница 67: ...P Extensions When VME extensions are enabled the IF modifying instruc tions that are normally trapped by the operating system are allowed to execute but they write and read the VIF bit rather than the...

Страница 68: ...ck It is set when an interrupt occurs for a Virtual 8086 program who s VIF bit is cleared The bit is checked by the processor when the program sub sequently attempts to set VIF Figure 3 6 and Table 3...

Страница 69: ...dified by the processor when a Virtual 8086 program running at less privilege than the IOPL attempts to modify the IF bit The VIF bit is used by the operating system to determine whether a maskable in...

Страница 70: ...VME Virtual Mode Extensions bit in CR4 bit 0 PVI Protected mode Virtual Interrupts bit in CR4 bit 1 IOPL I O Privilege Level bits in EFLAGS bits 13 12 Handler CPL Code Privilege Level of the interrupt...

Страница 71: ...0 0 CPL No Pushed PUSHFD 1 0 0 CPL No Pushed Pushed PUSHFD 1 0 0 CPL No Pushed Pushed POPF 1 0 0 CPL No Popped POPF 1 0 0 CPL No Not Popped POPFD 1 0 0 CPL No Popped Not Popped POPFD 1 0 0 CPL No Not...

Страница 72: ...0 3 No IF 0 No Change CLI 1 1 0 3 Yes STI 1 1 0 3 No IF 1 No Change STI 1 1 0 3 Yes PUSHF 1 1 0 3 No Pushed PUSHF 1 1 0 3 Yes PUSHFD 1 1 0 3 No Pushed Pushed PUSHFD 1 1 0 3 Yes POPF 1 1 0 3 No Popped...

Страница 73: ...ot Pushed Pushed into IF PUSHFD 1 1 1 3 No Pushed Pushed PUSHFD 1 1 1 3 Yes POPF 1 1 1 3 No Popped Not Popped POPF 1 1 1 3 No Not Popped Popped from IF POPFD 1 1 1 3 No Popped Not Popped POPFD 1 1 1 3...

Страница 74: ...STI 1 0 1 3 No3 No Change VIF 1 PUSHF 1 0 1 3 No Pushed Not Pushed PUSHF 1 0 1 3 No Pushed Not Pushed PUSHFD 1 0 1 3 No Pushed Pushed PUSHFD 1 0 1 3 No Pushed Pushed POPF 1 0 1 3 No Popped Not Popped...

Страница 75: ...TSS with the Interrupt Redirection Bitmap near the top The IRB contains 256 bits one for each possible software interrupt vector The most sig nificant bit of the IRB is located immediately below the...

Страница 76: ...n Bitmap IRB eight 32 bit locations 0 I O Permission Bitmap IOPB up to 8 Kbyte Operating System Data Structure Base Address of IOPB LDT Selector 0000h 0000h 0000h 0000h 0000h 0000h 0000h GS FS DS SS C...

Страница 77: ...IRB Interrupt Redirection Bit for a task from the Inter rupt Redirection Bitmap IRB in the tasks TSS GP 0 General protection exception with error code 0 IDT Protected Mode Interrupt Descriptor Table I...

Страница 78: ...Mode Extensions VME When a program is executed at CPL 3 it can set and clear its copy of the VIF flag without causing gen eral protection exceptions The only differences between the VME and PVI exten...

Страница 79: ...t of the registers 3 2 1 Machine Check Address Register MCAR The processor latches the address of the current bus cycle in its 64 bit Machine Check Address Register MCAR when a bus cycle error occurs...

Страница 80: ...rts PEN The MCTR can be read with the RDMSR instruction when the ECX register contains the value 01h Figure 3 9 and Table 3 7 show the formats of the MCTR register The contents of the register can be...

Страница 81: ...TSC EAX Lower 32 bits of TSC The TSC can be loaded with any arbitrary value 3 2 4 Array Access Register AAR The Array Access Register AAR contains pointers for testing the tag and data arrays for the...

Страница 82: ...ellaneous debugging functions The HWCR can be written or read with the WRMSR or RDMSR instruction when the ECX register contains the value 83h For details on the HWCR see Section 7 1 on page 7 3 3 3 N...

Страница 83: ...will execute the CPUID instruction For detailed instructions on processor and feature identification see the AMD Proces sor Recognition application note order 20734 Table 3 8 outlines the AMD K5 proc...

Страница 84: ...pcode if destination is a register Virtual 8086 mode Page fault The CMPXCHG8B instruction is an 8 byte version of the 4 byte CMPXCHG instruc tion supported by the 486 processor CMPXCHG8B compares a va...

Страница 85: ...ption MOV CR4 r32 0F22 Move to CR4 from register MOV r32 CR4 0F20 Move to register from CR4 Privilege CPL 0 Registers Affected CR4 32 bit general purpose register Flags Affected none Exceptions Genera...

Страница 86: ...CPL 0 However in Protected mode the RDTSC instruction can be used to read the counter at privilege levels higher than CPL 0 The required privilege level for using the RDTSC instruction is determined b...

Страница 87: ...for which the BUSCHK or PCHK signal was asserted For details see Section 3 1 1 on page 3 4 01h Machine Check Type Register MCTR This contains the cycle definition of the last bus cycle for which the...

Страница 88: ...EAX Lower 32 bits of MSR For the AAR this contains the data to be read writ ten All MSRs are 64 bits wide However the upper 32 bits of the AAR are write only and are not returned on a read EDX remains...

Страница 89: ...The RSM instruction should be the last instruction in any System Management Mode SMM service routine It restores the processor state that was saved when the SMI interrupt was asserted This instructio...

Страница 90: ...de description none 0FFF Illegal instruction reserved opcode Privilege Any level Registers Affected none Flags Affected none Exceptions Generated Real Virtual 8086 mode Invalid opcode Protected mode I...

Страница 91: ...hat is techniques common to both the AMD K5 and Pentium processors and techniques specific to the AMD K5 processor In general all optimization techniques used for the Pentium processor apply to any wi...

Страница 92: ...ly predicted branches have no cost mispredicted branches incur a three clock penalty Stack References Use ESP for references to the stack so that EBP remains available for general use Stack Allocation...

Страница 93: ...pipelined at one per cycle with 4 cycle latency in contrast to the Pentium processor s serialized 9 cycle time MUL has the same latency although the implicit AX usage of MUL prevents independent para...

Страница 94: ...l with floating point operations Locating Branch Targets Performance can be sensitive to code alignment especially in tight loops Locating branch targets to the first 17 bytes of the 32 byte cache lin...

Страница 95: ...tions for the floating point instructions The first column in these tables indicates the instruction mnemonic and operand types The fol lowing notations are used in the AMD K5 microprocessor docu ment...

Страница 96: ...here is a one cycle penalty for MROM entry point generation Each x86 instruction is converted into one or more ROPs The fourth column shows the execution unit and timing for each of the ROPs The ROP t...

Страница 97: ...z Result Cycle The relative cycle in which the result is returned on the result bus It is indicated only when the latency is greater than one cycle For stores it reflects the relative time that a stor...

Страница 98: ...ADD AL AX EAX imm 0_xx_0000010x_xxx_xxx F alu 1 1 ADD reg imm 0_0x_100000xx_000_xxx F alu 1 1 ADD mem imm 0_1x_100000xx_000_xxx F ld 1 1 alu 1 2 st 1 1 3 AND reg reg 0_0x_001000xx_xxx_xxx F alu 1 1 AN...

Страница 99: ...1010_111_xxx F alu1 1 1 BTC mem imm 1_1x_10111010_111_xxx F ld 1 1 alu1 1 2 st 1 1 3 BTR reg reg 1_0x_10110011_xxx_xxx F alu1 1 1 BTR mem reg 1_1x_10110011_xxx_xxx M alu1 1 1 alu 1 2 alu 2 3 ld 2 4 al...

Страница 100: ...lu 1 2 CMP mem reg 0_1x_0011100x_xxx_xxx F ld 1 1 alu 1 2 CMP AL AX EAX imm 0_xx_0011110x_xxx_xxx F alu 1 1 CMP reg imm 0_0x_100000xx_111_xxx F alu 1 1 CMP mem imm 0_1x_100000xx_111_xxx F ld 1 1 alu 1...

Страница 101: ...acement 0_xx_0111xxxx_xxx_xxx F brn 1 1 Jcc long displacement 1_xx_1000xxxx_xxx_xxx F brn 1 1 JCXZ short displacement 0_xx_11100011_xxx_xxx F brn 1 1 JMP long displacement 0_xx_11101001_xxx_xxx F brn...

Страница 102: ...eg 1_0x_1011111x_xxx_xxx F alu1 1 1 MOVSX reg mem 1_1x_1011111x_xxx_xxx F ld 1 1 alu1 1 2 MOVZX reg reg 1_0x_1011011x_xxx_xxx F alu 1 1 MOVZX reg mem 1_1x_1011011x_xxx_xxx F ld 1 1 alu 1 2 MUL AX AL r...

Страница 103: ...1 alu 1 2 st 1 1 3 POP reg 0_xx_01011xxx_xxx_xxx F ld 1 1 alu 1 1 POP reg 0_0x_10001111_000_xxx F ld 1 1 alu 1 1 POP mem 0_1x_10001111_000_xxx M ld 1 1 ld 1 1 st 2 2 3 alu 2 2 PUSH reg 0_xx_01010xxx_...

Страница 104: ...1 3 ROR reg imm 0_0x_1100000x_001_xxx F alu1 1 1 ROR mem imm 0_1x_1100000x_001_xxx F ld 1 1 alu1 1 2 st 1 1 3 ROR reg CL 0_0x_1101001x_001_xxx F alu1 1 1 ROR mem CL 0_1x_1101001x_001_xxx F ld 1 1 alu1...

Страница 105: ...1 2 st 1 1 3 SHLD reg reg imm 1_0x_10100100_xxx_xxx F alu1 1 1 alu1 2 2 SHLD mem reg imm 1_1x_10100100_xxx_xxx M alu1 1 1 ld 1 1 alu1 2 2 st 2 2 3 SHLD reg reg CL 1_0x_10100101_xxx_xxx F alu1 1 1 alu...

Страница 106: ...1 SUB reg mem 0_1x_0010101x_xxx_xxx F ld 1 1 alu 1 2 SUB mem reg 0_1x_0010100x_xxx_xxx F ld 1 1 alu 1 2 st 1 1 3 SUB AL AX EAX imm 0_xx_0010110x_xxx_xxx F alu 1 1 SUB reg imm 0_0x_100000xx_101_xxx F...

Страница 107: ...IMUL EAX EDI ECX 4 A i B i IMUL EBX EDI ECX 4 4 A i 1 B i 1 ADD ECX 2 increment index ADD EDX EAX even sum ADD EBP EBX odd sum CMP ECX EVEN_ARRAY_SIZE loop control JL mac_loop jump do final MAC here...

Страница 108: ...ct Internal Operations Timing Instruction Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 MOV EAX ESI ECX 4 L MOV EBX ESI ECX 4 4 L IMUL EAX EDI ECX 4 L M M M M IMUL EBX EDI ECX 4 4 L M M M M ADD ECX 2 A ADD E...

Страница 109: ...ing forwarded from the FPU itself however no format con version is required and operands are fast forwarded from the back end of a pipe to the front of any other pipe without the one cycle delay The a...

Страница 110: ...0_011_xxx F fpfill 1 2 4 fmv 1 2 4 alu 1 1 FCOMP real_32 0_1x_11011000_011_xxx F ld 1 1 fpfill 1 3 5 fmv 1 3 5 FCOMP real_64 0_1x_11011100_011_xxx M ld 1 1 ld 1 2 fpfill 1 4 6 fadd 1 4 6 FCOMPP 0_0x_1...

Страница 111: ...1010_011_xxx M ld 1 1 fpfill 1 3 7 fadd 1 3 7 fpfill 2 7 9 fmv 2 7 9 FILD int_16 0_1x_11011111_000_xxx F ld 1 1 fpfill 1 3 7 fadd 1 3 7 FILD int_32 0_1x_11011011_000_xxx F ld 1 1 fpfill 1 3 7 fadd 1 3...

Страница 112: ...ld 1 1 fpfill 1 2 5 fadd 1 2 5 st 1 5 6 FISTP int_64 0_1x_11011111_111_xxx M ld 1 1 ld 1 2 fpfill 1 2 5 fadd 1 2 5 st 2 3 6 st 2 4 7 FISUB int_16 0_1x_11011110_100_xxx M ld 1 1 fpfill 1 3 7 fadd 1 3 7...

Страница 113: ...2 4 fmv 1 2 4 nop 1 1 FMUL ST ST i 0_0x_11011000_001_xxx F fpfill 1 2 8 fmul 1 2 8 FMUL ST i ST 0_0x_11011100_001_xxx F fpfill 1 2 8 fmul 1 2 8 FMUL real_32 0_1x_11011000_001_xxx F ld 1 1 fpfill 1 3 7...

Страница 114: ...3 5 st 2 4 6 FSTP real_80 0_1x_11011011_111_xxx M ld 1 1 ld 1 2 fpfill 1 2 4 fmv 1 2 4 st 2 3 5 st 2 4 6 FSTP ST i 0_0x_11011x01_011_xxx F fpfill 1 2 4 fmv 1 2 4 FSUB ST ST i 0_0x_11011000_100_xxx F...

Страница 115: ...fadd 1 2 5 FTST 0_0x_11011001_100_xxx F fpfill 1 2 4 fmv 1 2 4 FUCOM ST i 0_0x_11011101_100_xxx F fpfill 1 2 4 fmv 1 2 4 FUCOMP ST i 0_0x_11011101_101_xxx F fpfill 1 2 4 fmv 1 2 4 nop 1 1 FUCOMPP 0_0...

Страница 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...

Страница 117: ...the architectural characteristics and functions of the signals and bus cycles The processor data sheet defines the setup and hold times for signals Throughout this chapter unless otherwise stated the...

Страница 118: ...avior of the AMD K5 processor s signals Figure 5 1 Signal Groups summarizes the processor s sig nals showing the functional groups to which each signal belongs Table 5 1 Summary of Signal Characterist...

Страница 119: ...PWT WB WT Clock Bus Arbitration CLK BF FRCMC IERR TCK TDI TDO TMS TRST BRDY BRDYC D63 D0 DP7 DP0 PCHK PEN EADS HIT HITM INV FERR IGNNE BUSCHK FLUSH INIT INTR NMI PRDY R S RESET SMI SMIACT STPCLK Test...

Страница 120: ...BOFF 1 or HLDA BF BF1 BF0 I Falling edge of RESET pullup BOFF I Every clock BRDY I Every clock from one clock after ADS until the last expected BRDY of the bus cycle BRDYC I same as BRDY pullup BREQ...

Страница 121: ...ock Falling edge triggered Recognized at next instruction boundary Acknowledged with Flush Acknowl edge special bus cycle FRCMC1 I Every clock in which RESET is asserted HIT O Every clock Changes stat...

Страница 122: ...triggered Recognized at next instruction boundary PCD O From ADS until last expected BRDY of the bus cycle BOFF 1 or HLDA PCHK O Two clocks after every BRDY of read cycles PEN I Every BRDY of read cyc...

Страница 123: ...p SMIACT O From one clock after the last expected BRDY of the bus cycle while EWBE is asserted until the return from SMM interrupt handler STPCLK1 I Every clock Level sensitive Recognized at next inst...

Страница 124: ...rrupt Acknow AHOLD Active BOFF Active HLDA Active Shutdown 33 Halt Stop Grant Stop Clock SMIACT Active RESET Active INIT Active PRDY Active Bus Arbitration AHOLD I 23 BOFF I BREQ O 38 HLDA O 39 35 HOL...

Страница 125: ...ADS7 I 43 43 43 43 1 43 43 HIT O 1 HITM O 1 INV I 43 43 43 43 1 43 43 Floating Point Errors FERR O IGNNE I Table 5 2 Conditions for Driving and Sampling Signals continued Signal Conditions under which...

Страница 126: ...rupts Interrupt Acknowledgments and Reset R S I See External Interrupts Interrupt Acknowledgments and Reset TCK I TDI I TDO O TMS I TRST I Bus and Processor Clock BF I 11 BF1 BF0 I 11 CLK I 11 Table 5...

Страница 127: ...nly meaningful during locked cycles 14 Includes Protected Virtual 8086 and Real modes unless otherwise indicated 15 During the Hardware Debug Tool HDT mode this signal is only meaningful for cache wri...

Страница 128: ...led but the only practical effect is to assert HLDA 36 Writebacks or writethroughs cannot occur when HLDA is asserted 37 During writebacks 38 During writebacks or writethroughs 39 Including writebacks...

Страница 129: ...ent assumes only the following definitions Interrupt The assertion or in the case of R S the driving Low of one of eight hardware input signals BUSCHK R S FLUSH SMI INIT NMI INTR or STPCLK Exception A...

Страница 130: ...uch interrupts The processor performs an interrupt by executing a microcode routine In this sense an interrupt acts like the execution of a complex instruction and the microcode routine has a comple t...

Страница 131: ...from generating another debug fault Table 5 3 shows the characteristics of interrupts and excep tions and the priority with which the processor recognizes them The term priority means two things here...

Страница 132: ...ce routine 8 INTR interrupt level sensitive 0 255 Interrupt acknowl edge special bus cycle Entry to service routine 9 STPCLK interrupt level sensitive none Stop Grant special bus cycle Negation of STP...

Страница 133: ...ted are not affected 5 1 4 Bus Signal Compatibility with Pentium Processor The differences in bus signal functions between the AMD K5 and Pentium processors are described in Section A 1 on page A 2 5...

Страница 134: ...ils The action of clearing A20 so that addresses above 1MB wrap around to addresses below 1 Mbyte simulates the behavior of the 8086 processor allowing the processor to run software designed for DOS A...

Страница 135: ...ncluding cache line fills caused by read misses cache writethroughs caused by write misses or write hits to lines in the shared state and cache accesses that occur while the processor does not control...

Страница 136: ...not provide an address The processor floats A31 A3 as outputs one clock after system logic asserts AHOLD or BOFF and in the same clock that the processor asserts HLDA As Inputs While AHOLD BOFF or HL...

Страница 137: ...rts writebacks at 32 byte aligned addresses address of the first quadword is xxxx_xx00h Thus A4 A3 are always 00b for writebacks System logic can derive memory and I O port select signals as well as m...

Страница 138: ...must be interpreted by system logic in con junction with the A20M input The processor does not control the complete bus during a writeback caused by an inquire cycle in these cases AHOLD BOFF or HOLD...

Страница 139: ...OFF or HOLD At the falling edge of RESET the states of BRDYC and BUS CHK control the drive strength on A21 A3 not including A31 A22 The drive strength is weak for all states of BRDYC and BUSCHK except...

Страница 140: ...bus cycles and interrupt acknowledge operations in the normal operating modes Real Protected and Virtual 8086 and in SMM or while PRDY is asserted While AHOLD is asserted and during the Shutdown Halt...

Страница 141: ...riteback or if BOFF or HOLD was used to obtain the bus During an inquire cycle that hits a modified cache line the processor asserts ADS as soon as two clocks after asserting HITM regardless of whethe...

Страница 142: ...serting EADS with the inquire address and the processor is driving a Branch Trace Message special bus cycle at the same time that AHOLD or BOFF is asserted the branch address information driven by the...

Страница 143: ...ntical copy of ADS In systems that would other wise place large capacitive loads on ADS the ADSC output can be used instead of ADS to distribute loads thereby increasing response time Driven and Float...

Страница 144: ...ee methods by which system logic can obtain control of the address bus to drive an inquire cycle AHOLD BOFF or HOLD AHOLD obtains control only of the address bus and allows another master or system lo...

Страница 145: ...sserted throughout an inquire cycle and any required writeback system logic must latch the inquire cycle address when it asserts EADS This is required so that if the inquire cycle hits a modified line...

Страница 146: ...he address bus so as to avoid deadlock contention for the bus Ground bounce spikes can be avoided by following two rules with respect to AHOLD Do not negate AHOLD in the same clock that BRDY is assert...

Страница 147: ...l number of 1 bits is even on AP and A31 A5 the address is con sidered free of error thus the term even parity If the total number of 1 bits is odd the address is considered to have an error The bit v...

Страница 148: ...ocks after system logic asserts EADS with an inquire address APCHK is driven under the same conditions in which EADS is sampled See the description of EADS on page 5 58 Details System logic can use AP...

Страница 149: ...to complete a bus cycle that had been initiated before AHOLD was asserted or for inquire cycle writebacks During the Shutdown Halt and Stop Grant states BE7 BE0 is driven only for inquire cycle write...

Страница 150: ...hich of the eight bytes on D63 D0 are valid During writebacks 32 byte four transfer bursts with CACHE asserted the processor drives all bits of BE7 BE0 Low to indicate that all eight bytes on D63 D0 a...

Страница 151: ...ium processor implement BE7 BE5 as outputs and BE4 BE0 as bidirectional signals On the AMD K5 processor however all eight BE7 BE0 signals are out puts only Table 5 6 Encodings For Special Bus Cycles B...

Страница 152: ...etails Table 5 7 shows the ratios between the processor clock and the bus clock CLK for the High and Low values of BF BF1 BF0 BF BF1 BF0 may be tied High or Low Due to the internal pullup resistor the...

Страница 153: ...alt or Stop Grant states or while AHOLD RESET INIT or PRDY is asserted BOFF is sampled but not effective when HLDA is asserted BOFF is not sampled during the Stop Clock state Details The assertion of...

Страница 154: ...signals floated The same set of signals is floated with HLDA The processor supports only one in progress bus cycle no pending bus cycles are buffered If the processor is driving a bus cycle when BOFF...

Страница 155: ...st BRDY and the cycles not yet run are restarted after BOFF is negated Thus system logic must keep track of all cycles in the locked operation that have completed before the assertion of BOFF and must...

Страница 156: ...5 Processor Technical Reference Manual 18524C 0 Nov1996 If BOFF is asserted when BUSCHK is asserted BOFF is recog nized and BUSCHK is ignored For a list of signals recognized while BOFF is asserted se...

Страница 157: ...had been initiated before AHOLD was asserted or for inquire cycle writebacks During the Shutdown Halt and Stop Grant states BRDY is sampled only for inquire cycle writebacks BRDY is not sampled when t...

Страница 158: ...r transfers of the burst All data transfers that are not performed as bursts are per formed as one or more single transfer cycles For write cycles EWBE must be asserted either with or after BRDY in or...

Страница 159: ...r writes In addition to the above uses of BRDY on the 486 processor BRDY on the AMD K5 and Pentium processors is used for both single transfer and burst cycles and it terminates special bus cycles Unl...

Страница 160: ...times Sampled BRDYC is sampled with the same timing as BRDY See the description of BRDY on page 5 41 Details See the description of BRDY on page 5 41 Unlike BRDY BRDYC has an internal pullup resistor...

Страница 161: ...terrupt acknowledge operations in the normal operating modes Real Protected and Virtual 8086 and in SMM or while AHOLD BOFF HLDA or PRDY is asserted BREQ is not driven in the Shutdown Halt Stop Grant...

Страница 162: ...ncluding cache writethroughs and writebacks I O cycles locked cycles spe cial bus cycles and interrupt acknowledge operations in the normal operating modes Real Protected and Virtual 8086 and in SMM o...

Страница 163: ...ll instruc tions remaining in the pipeline saves its state and gener ates a machine check exception 12h If the MCE bit is cleared to 0 the processor continues exe cution with the next instruction Afte...

Страница 164: ...BUSCHK is asserted and recognizes latched interrupts in prior ity order when BUSCHK is negated The MCE bit in CR4 which enables machine check exceptions during BUSCHK also enables machine check except...

Страница 165: ...PRDY is asserted The processor floats CACHE one clock after system logic asserts BOFF and in the same clock that the processor asserts HLDA Details The processor asserts CACHE for certain types of un...

Страница 166: ...e the processor asserts CACHE KEN is not a factor in determining the state of the PCD or CACHE signals The processor drives both PCD and CACHE before it knows the state of KEN For details see the desc...

Страница 167: ...four 32 bit transfers on the 486 processor they can be longer with narrower width memories Table 5 9 MESI State Transitions for Reads Signal or Event Result of Cache Lookup Read Miss Read Hit shared...

Страница 168: ...ed to its minimum when sys tem logic turns CLK off The processor enters its Stop Clock state when system logic asserts STPCLK thus entering the Stop Grant state and subsequently turns CLK off thus ent...

Страница 169: ...asserted or for inquire cycle writebacks During the Shut down Halt and Stop Grant states D C is driven only for inquire cycle writebacks D C is not driven during the Stop Clock state or while BOFF HLD...

Страница 170: ...4 Bus Interface AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996 During special bus cycles the processor drives D C 0 M IO 0 and W R 1 The cycles are then differentiated by BE7 BE0 and A31...

Страница 171: ...roughs and writebacks I O cycles locked cycles special bus cycles and interrupt acknowledge operations in the normal operating modes Real Protected and Virtual 8086 and in SMM or while PRDY is asserte...

Страница 172: ...1 A3 as described in Table 5 4 on page 5 21 During writebacks the processor drives all bits of BE7 BE0 Low to indicate that all eight bytes on D63 D0 are valid Write backs are addressed by A31 A3 but...

Страница 173: ...it values driven for each byte on DP7 DP0 are considered with the bit values driven for each byte on D63 D0 For example if the total number of 1 bits for the byte on D63 D56 is even for DP7 and D63 D5...

Страница 174: ...or Stop Grant state or while INIT or PRDY is asserted EADS is not sampled in the Stop Clock state or while RESET is asserted If BOFF and EADS are both asserted in the same clock that AHOLD is negated...

Страница 175: ...he processor asserts HLDA and simulta neously drive INV and a cache line address on A31 A5 The processor latches the address on A31 A5 when EADS is asserted 3 Wait two clocks watching for HITM and or...

Страница 176: ...t recognize this as a valid inquire cycle Inquire cycles can be implemented for every memory access by another caching master To do this system logic can generate EADS to the processor using the equiv...

Страница 177: ...les EADS in every clock including while the processor drives the address bus It can thus support inquire cycles every clock The AMD K5 and Pentium processors by comparison can sample EADS every other...

Страница 178: ...d assert EWBE when all external write buffers are empty thus indicating that the write to memory or I O has completed and that writes to the cache can take place Most systems tie EWBE Low asserted thu...

Страница 179: ...hen EWBE is asserted If system logic implements memory mapped I O as non cache able memory the standard method EWBE on the AMD K5 processor has the same effect on writes to memory mapped I O as does E...

Страница 180: ...086 and in SMM FERR is not driven during the Shutdown Halt Stop Grant or Stop Clock states or while RESET INIT or PRDY is asserted Details The processor asserts FERR on the instruction boundary of the...

Страница 181: ...Protected and Virtual 8086 and in SMM or in the Shutdown Halt or Stop Grant states or while AHOLD BOFF HLDA or RESET is asserted FLUSH is not sampled in the Stop Clock state or while INIT or PRDY is...

Страница 182: ...d ified lines in the data cache are written back to memory If writebacks are not required the INVD instruction or RESET can be used to invalidate all contents of the caches When FLUSH is recognized at...

Страница 183: ...serted during the Stop Grant state the signal is held pending until after the processor exits the Stop Grant state at which point it is acted upon No other interrupt or exception will intervene in a f...

Страница 184: ...aster controls instruction fetching and the checker mimics its behav ior by sampling the fetched instructions as they appear on the bus Both processors execute the instructions in lock step The checke...

Страница 185: ...signals are tied together so that they run the same pro gram The Functional Redundancy Checking mode can only be exited by the assertion of RESET Functional redundancy checking cannot be done in the H...

Страница 186: ...HIT HITM and INV Inquire cycle logic in systems with look aside caches can be simplified by monitoring only HITM and ignoring HIT This works because the resulting state of a hit line is determined onl...

Страница 187: ...n inquire cycle hit on an in progress cache line fill prior to the first BRDY and it will cache that line in the exclusive state if PWT 0 and WB WT 1 This may cause the line to be cached in the exclus...

Страница 188: ...Clock state or while RESET or INIT is asserted Details The processor asserts HITM when an inquire cycle address matches the address of a modified line in the processor s data cache The processor then...

Страница 189: ...e cycle An inquire cycle cannot hit a line involved in a locked operation Cached locations that are about to be accessed in locked opera tions are written back and invalidated before the locked opera...

Страница 190: ...after HOLD is negated HLDA is driven during cache hits in the normal operating modes Real Protected and Virtual 8086 and in SMM but writebacks wait until HLDA is negated HLDA is also driven in the Sh...

Страница 191: ...edging HOLD with HLDA System logic may assert EADS for an inquire cycle as early as one clock after the processor asserts HLDA The processor continues driving HLDA until two clocks after HOLD is negat...

Страница 192: ...d Stop Clock states or while AHOLD BOFF RESET INIT or PRDY is asserted HOLD is not sampled dur ing locked cycles or interrupt acknowledge operations Details The assertion of HOLD like BOFF but unlike...

Страница 193: ...drive its own cycles with ADS in the next clock after it negates HLDA During the time HOLD is asserted the pro cessor attempts to operate out of its cache If it can no longer do so it asserts BREQ con...

Страница 194: ...ing mode as the checker if FRCMC is asserted at RESET In this mode all of the processor s output and bidirectional signals except IERR and TDO are floated and tied to those of the master pro cessor Bo...

Страница 195: ...sam pled in the Shutdown Halt Stop Grant or Stop Clock states or while RESET INIT or PRDY is asserted System logic can drive the signal either synchronously or asyn chronously see the data sheet for...

Страница 196: ...point exception and continues with the execution of the target instruction FERR is not affected by the state of the NE bit or IGNNE FERR is always asserted at the instruction boundary of the tar get i...

Страница 197: ...p Grant states or while AHOLD BOFF HLDA or RESET is asserted INIT is not sampled in the Stop Clock state or while PRDY is asserted If INIT is asserted on the falling edge of RESET the processor perfor...

Страница 198: ...e buffer TLB 2 Reinitialize The processor reinitializes the following resources to reset values General purpose registers System registers 3 Jump To BIOS The processor jumps to the BIOS at address FFF...

Страница 199: ...h its nor mal boot process after the BIST completes whether the BIST passed or failed The processor recognizes BOFF HOLD AHOLD and R S while INIT is asserted but these signals will not intervene in th...

Страница 200: ...des Real Protected and Virtual 8086 and in SMM or in the Halt state INTR is not sampled in the Shutdown Stop Grant or Stop Clock states or while AHOLD BOFF or HLDA RESET INIT or PRDY is asserted INTR...

Страница 201: ...arries no useful information 3 Disable Interrupts The processor clears the IF bit in the EFLAGS register if a the processor is in Real mode or b the processor is in Protected mode and the interrupt ve...

Страница 202: ...y clearing the IF bit in EFLAGS Software may re enable INTR interrupts by setting IF to 1 again on entering the service routine In this context software interrupts include In Real mode any INTn instru...

Страница 203: ...96 AMD K5 Processor Technical Reference Manual INTR is not recognized if asserted while AHOLD BOFF or HLDA is asserted because the processor cannot drive the interrupt acknowledge operation and theref...

Страница 204: ...INV is typically asserted during a write by another caching master In such cases INV can be generated by watching W R from another bus master and asserting INV to the processor along with EADS only on...

Страница 205: ...is sampled only to complete a bus cycle already begun before the asser tion of AHOLD Details System logic typically maintains a specification of address cacheability in external registers that are wri...

Страница 206: ...the cache ways in which a potential line fill can be cached are already filled with valid entries the processor selects a line to replace during the line fill In the data cache if the selected line is...

Страница 207: ...IT or PRDY is asserted While AHOLD is asserted LOCK is driven only to complete a locked cycle that had been initiated before AHOLD was asserted The processor floats LOCK one clock after system logic a...

Страница 208: ...processor sets them so that the operating system can thereafter identify pages that have been accessed and updated XCHG Instruction When XCHG is used to swap a register with a memory location the acce...

Страница 209: ...LOCK asserted during the writeback System logic must recognize this case and know that the inquire cycle is snooping and writing back a different location than the one that is locked Locked operation...

Страница 210: ...nd exceptions are not recognized during locked operations The processor samples BUSCHK if it is asserted with any BRDY of a locked operation but the processor does not generate an enabled machine chec...

Страница 211: ...page 5 53 Details The processor accesses I O when it executes an I O instruction any of the INx or OUTx instructions The processor accesses memory when it fetches instructions or executes an instructi...

Страница 212: ...n the Shutdown Halt Stop Grant or Stop Clock states or while BOFF HLDA RESET INIT or PRDY is asserted While AHOLD is asserted NA is sampled only to complete a bus cycle already begun before the assert...

Страница 213: ...K5 processor recog nizes the INIT after leaving the Stop Grant state then it recog nizes the NMI prior to fetching any instructions Current implementations of the Pentium processor do not recognize t...

Страница 214: ...r vice routine The processor recognizes BOFF HOLD and AHOLD while NMI is asserted and these signals will intervene in the NMI ser vice routine The processor latches the assertion of any edge triggered...

Страница 215: ...FF HLDA RESET INIT or PRDY is asserted The processor floats PCD one clock after system logic asserts BOFF and in the same clock that the processor asserts HLDA Details If PCD is negated during read mi...

Страница 216: ...ed on page 5 105 The cache disable CD and not writethrough NW bits in CR0 are cleared to 0 for normal cacheable operation If a location is already cached before the operating system sets a PCD bit to...

Страница 217: ...e bit values driven on D63 D0 If the total number of 1 bits is even for DP7 DP0 and D63 D0 the byte is considered free of error thus the term even parity If the num ber of 1 bits is odd the byte is co...

Страница 218: ...tails If PEN is asserted when a data parity error is reported on PCHK the processor latches the physical address and cycle definition of the failed bus cycle in its 64 bit machine check address regist...

Страница 219: ...e accesses and I O cycles in the normal oper ating modes Real Protected and Virtual 8086 and in SMM in the Shutdown Halt or Stop Grant states or while AHOLD BOFF HLDA or RESET is asserted PRDY is not...

Страница 220: ...ssor Technical Reference Manual 18524C 0 Nov1996 Documentation on the HDT is available under nondisclosure agreement to test and debug developers For information con tact your AMD sales representative...

Страница 221: ...ns or in the Shutdown Halt or Stop Grant states except for writebacks due to inquire cycles and PWT is never driven during the Stop Clock state or while BOFF HLDA RESET or INIT is asserted The process...

Страница 222: ...writethrough PWT bit in one of three locations The selection of bits depends on the pro cessor s operating mode and the type of access as follows In Real mode and in Protected and Virtual 8086 modes...

Страница 223: ...he Shutdown Halt or Stop Grant states or while AHOLD BOFF HLDA RESET or INIT is asserted R S is not sampled during locked cycles special bus cycles or interrupt acknowledge operations or during the St...

Страница 224: ...et The processor recognizes AHOLD BOFF and HOLD while R S is Low and these signals will intervene in the HDT mode when PRDY is asserted However exceptions or interrupts are not recognized in the HDT m...

Страница 225: ...is asserted the processor performs its built in self test BIST before initialization and code fetching begin The processor samples RESET at all times except in the Stop Clock state and while INIT or P...

Страница 226: ...anslation look aside buffer TLB Branch prediction bits Clears the interrupt flag IF in EFLAGS to 0 3 Jump To BIOS The processor jumps to physical address FFFF_FFF0h the same entry point used after INI...

Страница 227: ...0_0000 FPU Exception Pointer 0_0000_0000_0000 CS F000 SS 0000 DS 0000 ES 0000 FS 0000 GS 0000 GDTR base 0000_0000 limit 0000 IDTR base 0000_0000 limit 0000 TR 0000 LDTR 0000 CR0 6000_0010 CR2 0000_000...

Страница 228: ...SET The operating system alone is responsible for controlling the state of A20M by writing to an external register provided for this purpose See the description of A20M on page 5 18 Because the proces...

Страница 229: ...s translation only begins to work in the normal Real mode manner when the first far jump is executed This jump loads the code segment register with a 16 bit segment selector This code segment load cau...

Страница 230: ...locked memory cycle already begun before the assertion of AHOLD The processor floats SCYC one clock after system logic asserts BOFF and in the same clock that the processor asserts HLDA Details For p...

Страница 231: ...misaligned the AMD K5 processor runs the bus cycles in the opposite order of the Pentium processor The AMD K5 processor trans fers the low address portion followed by the high address por tion instead...

Страница 232: ...ecognized on the instruction boundary associated with that BRDY SMI is sampled during memory cycles including cache writethroughs and writebacks cache accesses I O cycles locked cycles special bus cyc...

Страница 233: ...mpling EWBE asserted the proces sor asserts SMIACT to acknowledge the interrupt At that point system logic must ensure that all memory accesses during SMM are to the SMM memory space 4 Save Processor...

Страница 234: ...ory are simpler and may perform better However if SMM memory space overlaps main memory space that is cacheable FLUSH must be asserted when SMI is asserted so that memory accesses in SMM do not hit lo...

Страница 235: ...on restart and debug breakpoint trap the AMD K5 processor responds to the SMI first and postpones writing the exception related information to the stack until after the return from SMM via the RSM ins...

Страница 236: ...rupt before executing the first instruction of the INTR handler By contrast the AMD K5 processor recog nizes a pending NMI interrupt after returning via the IRET instruction from a prior interrupt The...

Страница 237: ...tion SMIACT is driven during memory cycles including cache writethroughs and writebacks cache accesses I O cycles locked cycles special bus cycles and interrupt acknowledge operations in the normal op...

Страница 238: ...es locked cycles special bus cycles and interrupt acknowledge operations in the normal operating modes Real Protected and Virtual 8086 and in SMM or in the Shutdown Halt or Stop Grant states STPCLK is...

Страница 239: ...h EWBE asserted the pro cessor drives a Stop Grant special bus cycle This cycle is identified by D C 0 M IO 0 W R 1 BE7 BE0 FBh and A31 A3 10h System logic must respond with BRDY 4 Stop Internal Clock...

Страница 240: ...eturns the processor to the Halt state Otherwise negation of STPCLK or assertion of RESET returns the processor to a normal operating mode Real Protected or Virtual 8086 or SMM If INIT is asserted in...

Страница 241: ...s until its phase lock loop is synchronized The latter takes several clocks see the data sheet for this specification The CLK can be driven with a different frequency and or the bus to processor clock...

Страница 242: ...STPCLK is negated The AMD K5 and Pentium processors differ in their support for STPCLK in the following ways In the Halt state the AMD K5 processor responds to STP CLK by entering the Stop Grant stat...

Страница 243: ...of TCK The outputs on TDO are driven valid on the falling edge of TCK When TCK stops on its falling edge the state of test latches in the processor are held Section 7 8 on page 7 19 summarizes the imp...

Страница 244: ...uring the shift_IR and shift_DR states TDI has an internal pullup resistor TDI is always sampled except while RESET or INIT is asserted Details Instructions are shifted into the processor on TDI durin...

Страница 245: ...shift_IR and shift_DR states It is floated at all other times TDO is always driven except when floated and while RESET or INIT is asserted Details Instructions are shifted out of the processor on TDO...

Страница 246: ...edge TMS has an internal pullup resistor TMS is always sampled except while RESET or INIT is asserted Details If TMS is asserted for five or more clocks the TAP controller enters its test reset logic...

Страница 247: ...esistor TRST is always sampled except while RESET or INIT is asserted Details When TRST is asserted the TAP controller enters its test reset logic state regardless of the controller state This action...

Страница 248: ...e the processor fetches an instruction or reads or writes a data operand it checks the associated code or data segment descriptor to verify that such action is permitted The execute E bit in the segme...

Страница 249: ...er misses the data cache or hits a shared line in the data cache the processor drives a 1 to 8 byte write cycle called a writethrough on the bus When an inquire cycle internal snoop FLUSH operation or...

Страница 250: ...ate Transitions for Reads Signal or Event Result of Cache Lookup Read Miss Read Hit shared exclusive modified CACHE PCD1 1 0 0 0 KEN 1 0 0 0 PWT 1 0 WB WT 0 1 Cache Line Fill 32 bytes no no yes yes ye...

Страница 251: ...cache write misses PWT 0 and WB WT 1 transition a shared line to an exclusive line The signal is not meaningful during cache read misses in the HDT mode because the caches are never filled in the HDT...

Страница 252: ...cycle accesses memory or an I O port W R specifies whether the cycle is a read or write The assertion of CACHE indicates that the processor is writing or is prepared to read a burst cycle consisting...

Страница 253: ...initiated bus cycle The processor guarantees at least one idle clock between consecutive bus cycles whether unlocked or locked This means that consecutive locked operations which consist of consecutiv...

Страница 254: ...ll nor mally occur immediately after the first bus cycle unless an interrupt or bus backoff intervenes If the misaligned transfer is run as a locked cycle the processor asserts both LOCK and SCYC thro...

Страница 255: ...d 10 4 4 4 for a DRAM page miss On a 50 MHz bus there is no change in timing for EDO DRAM but Page mode DRAM timing becomes 6 3 3 3 for a DRAM page hit and 8 3 3 3 for a DRAM page miss 5 3 5 Bus Cycle...

Страница 256: ...SH FRCMC and INIT Sampled on the falling edge of RESET TDI TDO TMS and TRST Sampled relative TCK For each signal in the timing diagrams the High level repre sents 1 the Low level represents 0 and the...

Страница 257: ...er ADS thus supporting very fast memory devices During the read cycle the processor drives PCD PWT and CACHE to indicate its caching and cache coherency intent for the access System logic returns KEN...

Страница 258: ...the failed bus cycle in its 64 bit machine check address register MCAR and its 64 bit machine check type register MCTR For details on such parity errors see the descriptions of PCHK and PEN on pages 5...

Страница 259: ...18524C 0 Nov1996 AMD K5 Processor Technical Reference Manual Figure 5 2 Single Transfer Memory Read and Write CLK A31 A3 ADS AP BE7 BE0 BRDY BREQ CACHE D C D63 D0 DP7 DP0 KEN M IO PCD PCHK PEN PWT W...

Страница 260: ...t asserting BRDY is that negating EWBE prevents only write requests but not asserting BRDY stalls the bus and prevents all requests More specifically if EWBE is negated with or after the last BRDY of...

Страница 261: ...g 5 145 18524C 0 Nov1996 AMD K5 Processor Technical Reference Manual Figure 5 3 Single Transfer Memory Write Delayed by EWBE Signal CLK A31 A3 ADS BE7 BE0 BRDY D C D63 D0 EWBE M IO W R CLK Write Write...

Страница 262: ...same as the protocol for read and write accesses to memory shown in Figure 5 2 except that M IO 0 Only data not code can be read or written from the I O address space The cycle definition for an I O...

Страница 263: ...to I O address 8Eh This transfer also crosses a doubleword bound ary so it is misaligned The processor writes the word to I O address 90h followed by the word to I O address 8Eh The AMD K5 processor p...

Страница 264: ...nterface AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996 Figure 5 5 Single Transfer Misaligned Memory and I O Transfers CLK A31 A3 ADS BE7 BE0 BRDY D C D63 D0 M IO SCYC W R CLK Read Read...

Страница 265: ...Burst Read Figure 5 6 shows two consecutive burst reads During burst reads CACHE and KEN both asserted with the first BRDY of a memory read the processor drives BE7 BE0 with ADS to identify the bytes...

Страница 266: ...EN were negated during the BRDY of the first transfer the read would terminate with the first quadword transfer thus becoming a single transfer read In this example the processor negates PWT indicatin...

Страница 267: ...n BRDY is asserted KEN and WB WT are validated by either NA or BRDY whichever comes first NA will not gen erate a pipelined cycle in the event that there are no pending internal cycles Figure 5 6 Burs...

Страница 268: ...5 152 Bus Interface AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996 Figure 5 7 Burst Read NA Sampled CLK A31 A3 ADS BE7 BE0 BRDY CACHE D C D63 D0 KEN M IO NA PWT W R WB WT CLK Read Read...

Страница 269: ...a snoop hits a data cache line in the modified state the line is written back to memory before being in validated WBINVD Instruction When the processor executes a WBINVD instruction it writes back al...

Страница 270: ...attempted burst read finds that all four cache ways for that address are filled with valid entries In this case the processor performs the following sequence 1 Copies the prior contents of the replace...

Страница 271: ...ng 5 155 18524C 0 Nov1996 AMD K5 Processor Technical Reference Manual Figure 5 8 Burst Writeback Due To Cache Line Replacement CLK A31 A3 ADS BE7 BE0 BRDY CACHE D C D63 D0 EADS KEN M IO PWT W R WB WT...

Страница 272: ...ween BOFF and AHOLD Due to its slow response time HOLD is usually considered only when backward compatibility with prior generation sub systems requires it or when the integrity of in progress bus cyc...

Страница 273: ...ted The resulting state of a cache line that is hit by an inquire cycle depends on the state of the INV signal at the time of the inquire cycle see Table 5 11 on page 5 71 If INV is negated the line r...

Страница 274: ...wo clocks at the time EADS is asserted AHOLD and BOFF can be asserted in con junction with each other without interfering with EADS recog nition as long as the sampling criteria for at least one of th...

Страница 275: ...r exclusive line in the cache as indicated by the assertion of HIT and the negation of HITM two clocks after the assertion of EADS The processor invalidates the cache line because sys tem logic assert...

Страница 276: ...ired writeback system logic must latch the inquire cycle address when it asserts EADS This is required so that if the inquire cycle hits a modified line the address used for the writeback need not be...

Страница 277: ...61 18524C 0 Nov1996 AMD K5 Processor Technical Reference Manual Figure 5 11 AHOLD Initiated Inquire Hit to Modified Line CLK A31 A3 ADS AHOLD BE7 BE0 BRDY D C D63 D0 EADS HIT HITM INV M IO W R CLK Rea...

Страница 278: ...ing cycles as early as two clocks after BOFF is asserted System logic or another bus mas ter may continue asserting BOFF for as long as it wants The processor has no way of breaking the hold While the...

Страница 279: ...ing 5 163 18524C 0 Nov1996 AMD K5 Processor Technical Reference Manual Figure 5 12 Basic BOFF Operation CLK A31 A3 ADS BE7 BE0 BOFF BRDY D C D63 D0 M IO W R CLK Read Aborted Cycle by Another Master Re...

Страница 280: ...modified cache line The writeback can not occur while BOFF is asserted however because the proces sor has floated its data and control outputs After BOFF is negated the processor writes back the modi...

Страница 281: ...1996 AMD K5 Processor Technical Reference Manual Figure 5 13 BOFF Initiated Inquire Hit to Modified Line CLK A31 A3 ADS BE7 BE0 BOFF BRDY CACHE D C D63 D0 EADS HIT HITM INV KEN M IO W R CLK Read abort...

Страница 282: ...ogic initiates an inquire cycle by asserting EADS and INV and driv ing an inquire address on A31 A5 The inquire cycle hits a shared or exclusive line HIT asserted and HITM negated two clocks after EAD...

Страница 283: ...4C 0 Nov1996 AMD K5 Processor Technical Reference Manual Figure 5 14 HOLD Initiated Inquire Hit to Shared or Exclusive Line CLK A31 A3 ADS BE7 BE0 BRDY CACHE D C D63 D0 EADS HIT HITM HLDA HOLD INV KEN...

Страница 284: ...ocks after EADS System logic negates HOLD in the clock after EADS and two clocks later one clock after HIT and HITM transition the processor negates HLDA As early as one clock after negating HLDA the...

Страница 285: ...ions which are also locked consist of a pair of read cycles with no operand modification between the cycles Locked operations generated by the LOCK instruction prefix cause LOCK to be asserted only du...

Страница 286: ...170 Bus Interface AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996 Figure 5 16 Basic Locked Operation CLK A31 A3 ADS BE7 BE0 BRDY CACHE D C D63 D0 KEN LOCK M IO W R CLK Read Write Read Wri...

Страница 287: ...example the processor also checks and if necessary sets the PTE Dirty D bit The general sequence both for PDE and PTE is as follows for accesses to a 4 Kbyte page The processor drives an unlocked read...

Страница 288: ...5 Processor Technical Reference Manual 18524C 0 Nov1996 Figure 5 17 TLB Miss 4 Kbyte Page CLK A31 A3 ADS BE7 BE0 BRDY CACHE D C D63 D0 EADS KEN LOCK M IO W R CLK Read PDE Read PTE Read PTE Write PTE R...

Страница 289: ...the locked operation Figure 5 18 shows the effect of BOFF intervening in a locked read write pair of bus cycles The example begins with the read while LOCK is asserted System logic asserts BOFF while...

Страница 290: ...AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996 Figure 5 18 Locked Operation with BOFF Intervention CLK A31 A3 ADS BE7 BE0 BOFF BRDY CACHE D C D63 D0 KEN LOCK M IO W R CLK Read Aborted Wr...

Страница 291: ...offset into an interrupt table System logic must return a BRDY in response to both cycles The processor inserts at least one idle clock between the locked reads System logic will typically not be abl...

Страница 292: ...d GDT Lookup Using the segment descriptor from the IDT the processor performs another read of the global descrip tor table GDT to look up the 8 byte code segment descrip tor This also appears as a bur...

Страница 293: ...C 0 Nov1996 AMD K5 Processor Technical Reference Manual Figure 5 19A Interrupt Acknowledge Operation Part 1 CLK A31 A3 ADS BE7 BE0 BRDY CACHE D C D63 D0 EADS INTR KEN LOCK M IO W R CLK INTR Asserted I...

Страница 294: ...ace AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996 Figure 5 19B Interrupt Acknowledge Operation Part 2 CLK A31 A3 ADS BE7 BE0 BRDY CACHE D C D63 D0 EADS INTR KEN LOCK M IO W R CLK IDT Lo...

Страница 295: ...24C 0 Nov1996 AMD K5 Processor Technical Reference Manual Figure 5 19C Interrupt Acknowledge Operation Part 3 CLK A31 A3 ADS BE7 BE0 BRDY CACHE D C D63 D0 EADS INTR KEN LOCK M IO W R CLK Write to stac...

Страница 296: ...les of the operation During the first cycle D31 D0 carries the EIP value of the source branch instruction Dur ing the second cycle D31 D0 carries the EIP value of the branch target instruction Table 5...

Страница 297: ...A31 A3 In this example BE7 BE0 FBh and A31 A3 0 so it is the special cycle the processor generates after executing a HLT instruction System logic must respond with BRDY All special bus cycles seriali...

Страница 298: ...fault vector 8 which amounts to a triple fault When the processor encoun ters such a triple fault it stops its activity on the bus and gen erates the special bus cycle for shutdown BE7 BE0 FEh System...

Страница 299: ...completing execution before the processor recognizes FLUSH on the next instruction retire ment boundary FLUSH causes the processor to write back all modified lines in its data cache Only one such writ...

Страница 300: ...Although the execution of INVD is not visible on the bus the lack of activity on the bus as the microcode invalidates the lines in the internal cache can be seen When all lines in both caches are inv...

Страница 301: ...line is written back immediately before being invalidated During such writebacks A31 A5 defines the address of a 32 byte location in memory to which the modified cache line will be written back After...

Страница 302: ...nce Manual 18524C 0 Nov1996 Figure 5 24B Cache Writeback and Invalidation Cycle WBINVD Instruction Part 2 CLK A31 A3 ADS BE7 BE0 BRDY CACHE D C D63 D0 KEN LOCK M IO W R CLK Cache Writeback and invalid...

Страница 303: ...e a BE7 BE0 DFh and system logic must respond by asserting BRDY to each of the cycles The first cycle identifies the branch source and the second identifies the branch target as shown in Table 5 24 Ta...

Страница 304: ...Interface AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996 Figure 5 25 Branch Trace Message Cycle CLK A31 A3 ADS BE7 BE0 BRDY CACHE D C D63 D0 KEN M IO W R CLK Branch trace Message specia...

Страница 305: ...cle when SMI was asserted the processor completes the bus cycle and waits until the system asserts the last expected BRDY and also asserts EWBE In Figure 5 26A a burst read is shown completing after S...

Страница 306: ...Processor Technical Reference Manual 18524C 0 Nov1996 Figure 5 26A Transition from Normal Execution to SMM Part 1 CLK A31 A3 ADS BE7 BE0 BRDY CACHE D C D63 D0 FLUSH KEN LOCK M IO SMI SMIACT W R CLK SM...

Страница 307: ...0 Nov1996 AMD K5 Processor Technical Reference Manual Figure 5 26B Transition from Normal Execution to SMM Part 2 CLK A31 A3 ADS BE7 BE0 BRDY CACHE D C D63 D0 FLUSH KEN LOCK M IO SMI SMIACT W R CLK B...

Страница 308: ...as or at sometime after it asserts STPCLK In Figure 5 27A a burst read is shown completing after STPCLK is asserted 3 Stop Grant Cycle After sampling both EWBE asserted the processor drives a Stop Gr...

Страница 309: ...v1996 AMD K5 Processor Technical Reference Manual Figure 5 27A Stop Grant and Stop Clock Modes Part 1 CLK A31 A3 ADS BE7 BE0 BRDY CACHE D C D63 D0 KEN LOCK M IO STPCLK W R CLK STPCLK Asserted Stop Gra...

Страница 310: ...Interface AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996 Figure 5 27B Stop Grant and Stop Clock Modes Part 2 CLK A31 A3 ADS BE7 BE0 BRDY CACHE D C D63 D0 KEN LOCK M IO STPCLK W R CLK Nor...

Страница 311: ...ro tected mode The 286 processor does not have an INIT input a transition from Protected mode to Real mode can only be made on the 286 processor by asserting RESET With the INIT signal however the ope...

Страница 312: ...sor Technical Reference Manual 18524C 0 Nov1996 Figure 5 28 INIT Initiated Transition from Protected Mode to Real Mode CLK A31 A3 ADS BE7 BE0 BRDY CACHE D C D63 D0 INIT KEN M IO RESET W R CLK INIT Ass...

Страница 313: ...ock refers both to the pro cessor s internal clock and to the bus clock CLK Thus each type of clock is explicitly differentiated in the descriptions that follow 6 1 Memory The processor can be configu...

Страница 314: ...system hard ware the boot address at FFFF_FFF0h which is accessed when RESET or INIT is asserted and the default addresses for SMM However other physical memory mapping requirements are imposed by BIO...

Страница 315: ...Extended expanded Memory Aliased Boot ROM High Memory BIOS ROM Device ROM Memory Mapped I O 4 Gbyte 1 Mbyte Hardware Alias 640 Kbyte DOS Kernel BIOS Data Interrupt Vectors Decimal Hexadecimal 0003_FF...

Страница 316: ...cal address 000F_FFF0h When RESET or INIT is asserted however the left shift is not done and the high 16 address bits are all set to 1 yielding the physical address FFFF_FFF0h Thereafter address trans...

Страница 317: ...this region and BIOS uses some of the RAM in this region to address locations that should not be cached such as memory mapped I O ports video disk net work and other devices Thus system logic typicall...

Страница 318: ...to initialize it with configuration parameters and the SMM service routine Thereafter the BIOS typically remaps the area from its default location in low memory to high or extended memory as shown in...

Страница 319: ...ontrols the cacheability of mem ory space If SMM memory is to be non cacheable KEN must be held negated from when SMI is asserted until SMIACT is negated If SMM memory is to be cacheable KEN must be a...

Страница 320: ...o that memory accesses in SMM do not hit locations cached from main memory If SMM memory is to be cacheable FLUSH must also be asserted with SMI when entering SMM and the SMM service routine must exec...

Страница 321: ...e in the L1 cache is guaranteed to be in the L2 cache The first principle L2 cache bigger guarantees that the L2 cache will have data that is not already in the L1 cache The second principle L2 cache...

Страница 322: ...reads and writes are given in Table 2 2 on page 2 19 Complete descrip tions of the signals that control cacheability and cache coher ency are given on the following pages CACHE Section 5 2 15 on page...

Страница 323: ...18 on page 5 135 The PWT bit also enters into this control but it is written by the operating system rather than system logic Alternatively system logic can force the on chip data cache to statically...

Страница 324: ...cache all cacheable reads in the exclusive state and all cacheable writes update only the cache In systems with multiple caching mas ters WB WT can be generated after inquire cycles to all other cach...

Страница 325: ...e in the instruction or data cache or it asserts both HIT and HITM if the address matches a modified line in the data cache If HITM is asserted the processor writes the modified line back to memory If...

Страница 326: ...e enough information to cache that line in the exclusive state this requires that HIT be monitored Lookaside caches must implement a signal with which to inform the memory controller that a processor...

Страница 327: ...ple caching masters For example if Master A controls the bus and attempts to write a memory location that is cached by Master B in a modified state a shared L2 controller could drive an inquire cycle...

Страница 328: ...essor can write back its modified line to main memory and the shared L2 cache Figure 6 3 BOFF Example A configuration in which both caching masters were on oppo site sides of a shared L2 look through...

Страница 329: ...tem logic from the L2 cache controller Figure 6 4 shows such a design A typical sequence for inquire cycles that hit modified lines in the processor s cache might be as follows 1 The master on the sy...

Страница 330: ...cal Reference Manual 18524C 0 Nov1996 Figure 6 4 AHOLD and BOFF Example System Bus Writeback EADS Other Bus Master Memory Access System Logic BOFF HITM 3 9 8 5 AMD K5 Processor Main Memory Look Throug...

Страница 331: ...can have the data exclusively and other caching masters must invalidate their copies The protocol allows other masters to determine whether the processor has a modified line in its L1 cache by drivin...

Страница 332: ...ive line The WB WT input has no effect This leaves the L1 and L2 caches as follows L1 cache line in the modified state L2 cache line in the modified state 5 During all subsequent writes to that line t...

Страница 333: ...r Technical Reference Manual Figure 6 5 Write Once Protocol WB WT 0 WB WT 1 WB WT 0 WB WT 0 Line Fill System Bus Other Bus Master System Logic AMD K5 Processor Main Memory Look Through L2 Cache 1 WB W...

Страница 334: ...ese invalidations are typically performed by the operating system or system logic during task or mode changes The invalidations are described on pages 5 65 and 5 180 The MESI state transitions for cac...

Страница 335: ...y an interrupt service routine It is designed for power management and other system control activities that can occur transparently to conventional operating systems like DOS and Windows The code and...

Страница 336: ...ssor Interrupt vectors use the Real mode interrupt vector table but see Section 6 3 8 on page 6 32 The IF flag in EFLAGS is cleared INTR not recognized The NMI interrupt is disabled The TF flag in EFL...

Страница 337: ...s of any reserved locations in the state save area are not necessarily the same between the AMD K5 processor and the Pentium or 486 processors Table 6 1 Initial State of Registers in SMM Register Init...

Страница 338: ...served read only FFC0 LDTR 16 upper 16 reserved read only FFBC GS 16 upper 16 reserved read only FFB8 FS 16 upper 16 reserved read only FFB4 DS 16 upper 16 reserved read only FFB0 SS 16 upper 16 reser...

Страница 339: ...read only FF4C DS Base 32 read only FF48 DS Limit 20 upper 12 reserved read only FF44 SS Attributes 12 upper 20 reserved read only FF40 SS Base 32 read only FF3C SS Limit 20 upper 12 reserved read on...

Страница 340: ...ress During RESET the processor sets the code segment CS base address for the SMM memory area the SMM Base Address to its default 0003_0000h The SMM base address at offset FEF8 in the SMM state save a...

Страница 341: ...ocation feature is compatible with the Pentium processor s analogous feature The following pseudo code implements a relocatable SMM base address in BIOS begin if SMI Handler is to be Relocated then se...

Страница 342: ...tered from Halt state Before return from SMM the halt restart slot can be written as Bits 15 1 Undefined Bit 0 Point of return from SMM 1 return to Halt state 0 return to state specified by SMM state...

Страница 343: ...uction and if so whether the trapped I O instruction should be re executed on return from SMM This is sometimes called the I O instruction restart func tion Re executing a trapped I O instruction is u...

Страница 344: ...o be restarted then if valid I O instruction test offset FFA4 then set I O restart slot offset FF00 to 00FFh end During a simultaneous SMI I O instruction trap and debug breakpoint trap the AMD K5 pro...

Страница 345: ...ummy interrupt All other exceptions and interrupts within SMM are fully compatible with those supported by the Pentium processor in SMM The IF flag in EFLAGS is cleared automatically when the pro cess...

Страница 346: ...on would be communicated to the power man agement logic which would assert STPCLK to the processor and optionally stop driving CLK to the processor and other logic For details on SMI and STPCLK see pa...

Страница 347: ...ts phase lock loop still runs its key internal logic is still clocked most of its inputs and outputs retain their last state except D63 D0 and DP7 DP0 which are floated and it still responds to input...

Страница 348: ...ntrol State Transitions EADS EADS HLT Instruction Stop Grant State Normal Mode Real Virtual 8086 Protected SMM Halt State Stop Clock State RESET SMI INIT or INTR Asserted Stop Grant Inquire State STPC...

Страница 349: ...state the majority of the processor s internal clock distribution and all internal pullup resistors are disabled However its phase lock loop still runs its key internal logic is still clocked most of...

Страница 350: ...n The CLK can be driven with a different frequency and or the bus to processor clock ratio can be changed on the BF input s upon restarting CLK 6 4 6 Clock Control Compatibility with Pentium Processor...

Страница 351: ...design recommendations apply to power con nections between the processor and the system board Connect all VCC pins to a VCC plane on your system board Connect all VSS pins to a GND plane on your syst...

Страница 352: ...e asserted as VCC is ramping toward normal operating volt age Figure 6 7 shows this timing After VCC and CLK reach specification RESET must be asserted for a minimum of 1 ms to allow the phase lock lo...

Страница 353: ...acitors Use ceramic capacitors with low equivalent series resis tance ESR ratings at high frequencies and a minimum voltage rating of 6 V for all other capacitor values Place some capacitors very near...

Страница 354: ...ith some type of heatsink device Typ ically the heatsink is combined with an airflow device such as a fan In general the trade off is heat sink size and cost versus airflow quantity and temperature A...

Страница 355: ...heck the specification for any TTL parts on the board for thermal considerations 6 9 Design Support and Peripheral Products AMD field application engineers FAEs can help you solve system design proble...

Страница 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...

Страница 357: ...e AMD K5 processor to float all of its output and bidirectional signals Cache and TLB Testing The Array Access Register AAR supports writes and reads to any location in the tag and data arrays of the...

Страница 358: ...mode is a collection of signals registers and processor microcode that is enabled when external debug logic drives R S Low or loads the AMD K5 processor s Test Access Port TAP instruction register wi...

Страница 359: ...unc tions The WRMSR and RDMSR instructions access the HWCR when the ECX register contains the value 83h as described in Section 3 3 5 on page 3 33 Figure 7 1 and Table 7 1 show the format and fields o...

Страница 360: ...Branch Prediction Disables branch prediction 0 enabled 1 disabled 4 reserved 3 1 DC Debug Control Debug control bits 000 Off disable HWCR debug control 001 Enable branch tracing messages See Section 7...

Страница 361: ...ests its caches during the BIST EADS should not be asserted during a BIST The processor accesses the phys ical tag array during BISTs and these accesses can conflict with inquire cycles 7 2 1 Normal B...

Страница 362: ...st Access Port TAP BIST The TAP BIST performs all of the functions of the normal BIST up to and including the PLA signature test in the exact manner as the normal BIST However after the PLA test the t...

Страница 363: ...ted state system board traces and connections can be tested for integrity and driveability The Output Float Test mode can only be exited by asserting RESET again On the AMD K5 and Pentium processors F...

Страница 364: ...ay test data to be read or written The WRMSR and RDMSR instruc tions access the AAR when the ECX register contains the value 82h as described in Section 3 3 5 on page 3 33 Figure 7 2 shows the format...

Страница 365: ...bits For the 4 Kbyte TLB the way and set specify one of the 128 TLB entries For the 4 Mbyte TLB one of only four entries is speci fied Bits 7 0 of every array pointer encode the array ID which iden t...

Страница 366: ...pointer or the physical tag array ECh in bits 7 0 of the array pointer If the linear tag array E1h were accessed the data read or written includes the tag and the status bits The details of the valid...

Страница 367: ...v1996 AMD K5 Processor Technical Reference Manual Figure 7 4 Test Formats Data Cache Data EDX Array Pointer 0 31 30 29 28 27 0 0 Array ID E0h Way 0 0 0 0 0 0 0 0 0 Set 0 0 EAX Test Data E0h Data 0 Val...

Страница 368: ...Prediction Bits 8 7 0 11 12 19 20 31 30 29 28 27 0 0 Array ID E5h EDh E6h E7h Way 0 0 0 0 0 0 0 0 Set 0 0 0 0 EAX Test Data E5h Linear Tag EDh Physical Tag E6h Valid Bits 0 19 20 31 0 0 0 0 0 0 0 0 0...

Страница 369: ...Technical Reference Manual Figure 7 6 Test Formats Instruction Cache Instructions EDX Array Pointer 0 31 30 29 28 27 0 0 Array ID E4h Way 0 0 0 0 0 0 0 0 Set 0 EAX Test Data E4h Instruction Bytes 7 20...

Страница 370: ...7 7 Test Formats 4 Kbyte TLB EDX Array Pointer 0 31 30 29 28 27 0 0 Array ID E8h E9h Way 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Set EAX Test Data E8h 4 Kbyte Page and Status E9h 4 Kbyte Linear Tag 0 0 0 0 0 0...

Страница 371: ...rmats 4 Mbyte TLB EDX Array Pointer 0 31 30 29 28 27 0 0 Array ID EAh EBh Entry 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EAX Test Data EAh 4 Mbyte Page and Status EBh 4 Mbyte Linear Tag 0 0 0 0 0 0 0 0...

Страница 372: ...need to embed breakpoints in code and allow debugging of ROM as well as RAM For details on the standard 486 debug functions and registers see the AMD documentation on the Am486 processor or other comm...

Страница 373: ...6 Branch Tracing Branch tracing is enabled by writing bits 3 1 with 001b and set ting bit 5 to 1 in the Hardware Configuration Register HWCR as described in Section 7 1 on page 7 3 When thus enabled...

Страница 374: ...er s signals The master controls instruction fetching and the checker mimics its behav ior by sampling the fetched instructions as they appear on the bus Both processors execute the instructions in lo...

Страница 375: ...sts solely of reporting one or more errors The particular type of error or the instruction causing an error is not reported The arrangement works because the processor is entirely deterministic Specul...

Страница 376: ...or read from the processor boundary The register is controlled with the EXTEST and SAMPLE in structions Device Identification Register DIR Contains the codes for manufacturer s identification part num...

Страница 377: ...isters are updated when the controller exits the update state update_DR or update_IR The sections below describe only those aspects of the IEEE standard that are implemented uniquely by the AMD K5 pro...

Страница 378: ...tion is described below Any instruction encodings not shown in Table 7 6 select the BYPASS instruction Table 7 6 Public TAP Instructions Instruction Encoding Register Description EXTEST 00000 BSR As d...

Страница 379: ...e is a collection of signals regis ters and processor microcode that is enabled when external debug logic drives R S Low or loads the processor s Test Access Port TAP instruction register with the USE...

Страница 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...

Страница 381: ...es are compatible with the Pentium processor Package and pinout Electrical interface including bus cycles AC and DC parameters interrupt handling power saving etc Instruction set programming model mem...

Страница 382: ...Address Strobe ADSC x x Address Strobe AHOLD x x Address Hold AP x x Address Parity APCHK x x Address Parity Check APICEN x APIC Enable High during RESET PICD1 x PIC Data 1 BE7 BE0 x x Byte Enables Fl...

Страница 383: ...s FRCMC x x Functional Redundancy Checking Master Checker HIT x x Inquire Hit HITM x x Inquire Hit to Modified Line HLDA x x Hold Acknowledge HOLD x x Hold IERR x x Internal Error IGNNE x x Ignore Num...

Страница 384: ...RESET x x Reset SCYC x x Misaligned Transfer SMI x x System Management Interrupt SMIACT x x System Management Interrupt Active STPCLK x x Stop Clock TCK x x Test Access Port TAP Clock TDI x x Test Ac...

Страница 385: ...nlocked reads to get the descriptor If the Accessed bit needs to be set two locked reads will be followed by one 1 byte locked write For updates to the Busy bit in the TSS descriptor the AMD K5 proces...

Страница 386: ...d cycles in the reverse order of the Pentium processor Split I O write cycles occur in the same order on both processors A 2 4 Halt Cycle after FLUSH When halted the AMD K5 processor reruns a Halt spe...

Страница 387: ...Strength medium and strong The only way to get the AMD K5 processor Drive Strength 2 is to select the Pentium processor Drive Strength strong as shown in the table above AMD K5 Processor Model 0 Rev F...

Страница 388: ...ed or invalid depending on the state of the INV pin If KEN is sampled inac tive the line is not cached regardless of the state of the INV pin In treating the snoop as a miss the Pentium processor nega...

Страница 389: ...le is restarted after the deassertion of BOFF and AHOLD The behavior of snoops to the linefill buffer before cacheabil ity is determined is described in Section A 3 1 A 3 3 Snoop Before Write Hit to I...

Страница 390: ...DY or NA of the write and if it is High the line changes state from shared to exclusive Subse quent writes to the same line change the state of the line from exclusive to modified and do not go extern...

Страница 391: ...the accessed bit being set for a page that is not actually used The AMD K5 processor does not perform specu lative TLB refills A 4 2 Page Fault Encountered by a Load Store Type of Instruction On a re...

Страница 392: ...eakpoint Trap On a simultaneous I O SMI trap and debug breakpoint trap the AMD K5 processor responds to the SMI first and postpones writing the fault frame for the debug trap to the stack until after...

Страница 393: ...entium processor documentation A 5 5 NMI Recognition during SMM When operating in SMM an NMI request should not be recog nized unless an enabled INTR is encountered Both the AMD K5 and Pentium process...

Страница 394: ...ult The Pentium and 486 processors prioritize the limit violation fault A 6 2 Task Switch On a task switch the AMD K5 processor sets the busy bit of the incoming task after storing the outgoing TSS ac...

Страница 395: ...egisters are enabled On instructions that do multiple memory accesses the Pentium processor sets the DR6 B bits for matching debug registers that are both enabled and disabled The AMD K5 processor onl...

Страница 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...

Страница 397: ...5 137 BF 5 10 5 36 BIST 7 5 Bit Scan 4 4 Bit Test 4 4 Bits A 5 171 accessed 5 171 D 5 171 DBP 7 4 DC 7 4 DDC 7 4 DE 3 3 DIC 7 4 dirty 5 171 DSPC 7 4 G 3 8 3 11 GPE 3 3 MCE 3 3 3 4 PS 3 8 3 11 PSE 3 3...

Страница 398: ...l 5 9 6 9 data 2 15 design 6 8 disable 5 99 dual tagged 2 16 enable KEN 5 89 enabling 2 13 FLUSH 5 65 hits 5 8 inquire cycles 2 21 instruction 2 14 internal snooping 2 22 invalidation 2 20 5 88 6 22 i...

Страница 399: ...ions Also see Interrupts 5 13 Execution branch unit 2 10 floating point unit 2 10 integer shift units 2 9 load store units 2 10 pipeline 2 4 speculative 2 10 timing 4 5 units 2 8 External Interrupts 5...

Страница 400: ...erands 4 2 MOV to from CR4 3 31 move and convert 4 3 multiplies 4 3 operands 4 2 optimization 4 1 performance 4 1 prefixes 4 3 RDMSR 3 33 RDTSC 3 32 RSM 3 35 serializing 2 8 shifts 4 2 short forms 4 1...

Страница 401: ...g 2 28 read write reordering 2 27 segmentation 2 27 SMM 6 5 stack 4 2 storage model 2 26 TLBs 2 28 MESI State 2 16 2 18 inquire cycles 5 71 reads 5 134 writes 5 135 Microcode 2 7 Misalignment order of...

Страница 402: ...e level 5 140 Probe Mode 5 103 5 107 7 23 Probe Ready 5 103 Protected Virtual Interrupts 3 3 3 24 PS 3 8 3 11 PSE 3 3 PTE 3 10 Public TAP Instructions 7 22 PVI 3 3 3 24 PWT 5 9 5 105 5 150 R R S 5 10...

Страница 403: ...10 5 15 5 16 5 84 5 175 INV 5 9 5 88 KEN 5 9 5 89 5 136 5 150 LOCK 5 8 5 91 M IO 5 8 5 95 5 136 NA 5 8 5 96 5 150 NMI 5 10 5 15 5 16 5 97 outputs at RESET 5 112 parity 5 8 5 9 PCD 5 9 5 99 PCHK 5 9 5...

Страница 404: ...5 8 5 52 5 125 5 192 6 38 Stop Grant Inquire State 5 124 6 37 Stop Grant State 5 8 5 35 5 124 5 180 5 192 6 37 7 4 Storage EWBE 2 26 model 2 26 ordering 2 26 read write reordering 2 27 Store 2 15 2 2...

Страница 405: ...3 3 3 12 VME 3 3 3 12 W W R 5 8 5 132 5 136 Wait States 5 41 WB WT 5 9 5 133 5 150 WBINVD 5 35 5 180 Weak Memory Order 2 26 Writebacks xvii 2 18 2 20 5 105 5 133 5 153 6 10 buffers 2 8 2 22 2 25 2 26...

Страница 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...

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