Acromag ACPS3320 User Manual Download

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ACPS3320 CompactPCI-Serial AcroPack Carrier Board

USER’S MANUAL

ACROMAG INCORPORATED

30765 South Wixom Road

Wixom, MI 48393-2417 U.S.A.

Tel: (248) 295-0310

Email: [email protected]

Data and specifications are subject to change without notice.

8501141A

Summary of Contents for ACPS3320

Page 1: ...ard USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road Wixom MI 48393 2417 U S A Tel 248 295 0310 Email solutions acromag com Copyright 2019 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8501141A ...

Page 2: ...R USE 7 UNPACKING AND INSPECTION 7 BOARD CONFIGURATION 7 Power and Cooling Considerations 8 Carrier Fuses 9 ACROPACK MODULE INSTALLATION 9 FIELD GROUNDING CONSIDERATIONS 10 CONNECTORS 10 AcroPack Field I O Connectors 10 Mini PCIe Connectors 13 CompactPCI Serial Backplane Connections 14 JTAG Programming Debug Connector 18 3 THEORY OF OPERATION 18 PCIe Switch 19 DC DC Converter 19 Slot Addressing 19...

Page 3: ...RTM Rear Transition Accessory Module 25 7 1 Ordering Information 25 SIGNAL INTERFACE PRODUCTS 25 Cable 25 Termination Panel 26 7 2 Specifications 26 Physical Configuration 26 Connectors 26 7 2 1 rJ2 CPCI S Connector 26 7 2 2 rJ3 CPCI S Connector 27 7 2 3 J1 Field I O Connector 28 Isolation 31 CPCI S Compliance 31 ENVIRONMENTAL 31 EMC Compliance 31 Vibration and Shock Standard 31 Reliability Predic...

Page 4: ...emarks registered trademarks trade names and service marks are the property of their respective owners Radio Frequency Interference Statement This is a Class A product In a domestic environment this product may cause radio interference in which case the user may find it necessary to take adequate corrective measures Environmental Protection Statement This product has been manufactured to satisfy e...

Page 5: ...carrier and AcroPack module from others when multiple instances of the same carrier and or module are used in a system JTAG Programming Header A standard 14 pin Xilinx JTAG programming header is provided for programming and debugging the FPGA on some AcroPack modules The JTAG ports of the two AcroPack modules are daisy chained Individually Fused Power Fused 1 5V 3 3V 5V 12V and 12V DC power is pro...

Page 6: ...The software is implemented as a library of C functions which link with existing user code to make possible simple control of all Acromag AcroPack modules Linux Acromag provides a software product consisting of Linux software This software Model APSW API LNX is composed of Linux libraries for all AcroPack modules VPX I O board products and PCIe I O Cards The software is implemented as a library of...

Page 7: ...omag Limited Warranty WARNING This AcroPack carrier does not provide isolation between the AcroPack Field I O signals and the host It is not intended to be used with isolated AcroPack modules UNPACKING AND INSPECTION Upon receipt of this product inspect the shipping carton for evidence of mishandling during transit If the shipping carton is badly damaged or water stained request that the carrier s...

Page 8: ...erature rise above the maximum operating temperature The lack of air circulation within some CPCI S chassis could be a cause for some concern The dense packing of the AcroPack modules to the carrier board alone results in elevated module and carrier board temperatures and the restricted air flow within the chassis aggravates this problem Adequate air circulation must be provided to prevent a tempe...

Page 9: ...ni PCIe cards may require 3 3V Aux to power the module For a site using such a module the 3 3V fuse will need to be removed and the 3 3 Aux fuse will need to be installed along with a regulator to convert 5V standby from the CPCI S backplane to 3 3V Aux Return the carrier board to Acromag to remove and install these parts ACROPACK MODULE INSTALLATION Power should be removed from the carrier board ...

Page 10: ...AcroPack Field I O Connectors The field side connector of AcroPack modules mate to Samtec SS5 50 3 00 L D K TR socket connectors on the carrier board This provides excellent connection integrity due to the gold plating in the mating area M2 5 screws and spacers provide additional stability for harsh environments The functions of each of the Field I O signals are defined by the installed AcroPack m...

Page 11: ... isolation 27 27 Reserved isolation 30 30 Field I O 15 29 29 Field I O 16 32 32 Reserved isolation 31 31 Reserved isolation 34 34 Field I O 17 33 33 Field I O 18 36 36 Reserved isolation 35 35 Reserved isolation 38 38 Field I O 19 37 37 Field I O 20 40 40 Reserved isolation 39 39 Reserved isolation 42 42 Field I O 21 41 41 Field I O 22 44 44 Reserved isolation 43 43 Reserved isolation 46 46 Field ...

Page 12: ...eld I O 32 64 64 Reserved isolation 63 63 Reserved isolation 66 66 Field I O 33 65 65 Field I O 34 68 68 Reserved isolation 67 67 Reserved isolation 70 70 Field I O 35 69 69 Field I O 36 72 72 Reserved isolation 71 71 Reserved isolation 74 74 Field I O 37 73 73 Field I O 38 76 76 Reserved isolation 75 75 Reserved isolation 78 78 Field I O 39 77 77 Field I O 40 80 80 Reserved isolation 79 79 Reserv...

Page 13: ...47 93 93 Field I O 48 96 96 Reserved isolation 95 95 Reserved isolation 98 98 Field I O 49 97 97 Field I O 50 100 100 Reserved isolation 99 99 Reserved isolation Mini PCIe Connectors The AcroPack Mini PCIe connectors mate to TE Connectivity 1759457 1 connectors on the carrier board AcroPack locations are labeled on the board for easy identification Pin assignments for these connectors are based on...

Page 14: ... LED_WPAN LED_WLAN LED_WWAN W_DISABLE COEX1 COEX2 UIM_C4 UIM_C8 UIM_VPP UIM_RESET UIM_CLK UIM_DATA UIM_PWR 2 TDI is tied to TDO on modules that do not use JTAG 3 5 12 and 12 Volt power supplies have been assigned to pins that are reserved in the mini PCIe specification Remove the fuses on these power supplies for mini PCIe cards from other vendors that cannot tolerate power applied to these reserv...

Page 15: ...KIN 05 1_PE_Rx00 1_PE_Rx00 GND 06 GND 1_PE_Rx02 1_PE_Rx02 G H I 01 12V 12V GND 02 GND RST WAKE_OUT 03 SATA_SDI SATA_SDO GA2 04 GND 1_SATA_Tx 1_SATA_Tx 05 1_PE_Tx01 1_PE_Tx01 GND 06 GND 1_PE_Tx03 1_PE_Tx03 J K L 01 12V 12V GND 02 GND PCIE_EN SYSEN 03 SATA_SCL SATA_SL GA3 04 GND 1_SATA_Rx 1_SATA_Rx 05 1_PE_Rx01 1_PE_Rx01 GND 06 GND 1_PE_Rx03 1_PE_Rx03 Notes Table 3 1 Hash is used to indicate an acti...

Page 16: ...Site A Field I O 23 Site A Field I O 24 07 Site A Field I O 15 Site A Field I O 16 GND 08 GND Site A Field I O 7 Site A Field I O 8 G H I 01 N C 1 N C 1 GND 02 GND N C 1 N C 1 03 Site A Field I O 45 Site A Field I O 46 GND 04 GND Site A Field I O 37 Site A Field I O 38 05 Site A Field I O 29 Site A Field I O 30 GND 06 GND Site A Field I O 21 Site A Field I O 22 07 Site A Field I O 13 Site A Field ...

Page 17: ...te B Field I O 19 Site B Field I O 20 07 Site B Field I O 11 Site B Field I O 12 GND 08 GND Site B Field I O 3 Site B Field I O 4 G H I 01 N C 1 N C 1 GND 02 GND N C 1 N C 1 03 Site B Field I O 45 Site B Field I O 46 GND 04 GND Site B Field I O 37 Site B Field I O 38 05 Site B Field I O 29 Site B Field I O 30 GND 06 GND Site B Field I O 21 Site B Field I O 22 07 Site B Field I O 13 Site B Field I ...

Page 18: ...alent The pin assignment for P9 is shown in 7 A bypass circuit is included that will detect a vacant AcroPack site and close a switch to bypass the TDI and TDO signals A CPLD on the carrier is included in the JTAG chain The Xilinx Vivado tools can detect the presence of the CPLD in the JTAG chain and skip it when accessing the FPGAs on the AcroPack modules Table 7 JTAG Programming Debug Connector ...

Page 19: ... TCK pin on all target ISP devices sharing the same data stream TDO JTAG Test Data Out This pin is the serial data stream received from the TDO pin on the last device in a JTAG chain TDI JTAG Test Data In This pin outputs the serial data stream transmitted to the TDI pin on the first device in a JTAG chain 3 3V The target reference voltage VREF is 3 3 Volts GND Ground 3 THEORY OF OPERATION This se...

Page 20: ...on the geographical addressing signals GA0 GA3 from the backplane The slot address is 5 bits long and consists of 1 bit to identify the site on the carrier where the AcroPack modules is installed and 4 bits that are determined by the GA signals The CPLD will serialize the slot address and transmit the address to the AcroPack module as requested by the AcroPack module The process of reading the slo...

Page 21: ...AcroPack Series ACPS3320 CompactPCI Serial Carrier Board 21 fuse locations are shown in Figure 1 The current rating for each of the fuses is listed in the Fuses paragraph in section 5 ...

Page 22: ...tation of your carrier board to verify that it is correctly configured Replacement of the module with one that is known to work correctly is a good technique to isolate a faulty module CAUTION POWER MUST BE TURNED OFF BEFORE REMOVING OR INSERTING BOARDS WHERE TO GET HELP If you continue to have problems your next step should be to visit the Acromag website at https www acromag com Our website cont...

Page 23: ... signals and the host It is not intended to be used with isolated AcroPack modules Power Board power requirements are a function of the installed AcroPack modules This specification below lists current specified is for the ACPS3320 carrier board only 12 Volts 8 0 292A Typical Add the current for each of the AcroPack modules to calculate the total current required from each supply The carrier is de...

Page 24: ...IEC 61000 4 4 Surge Immunity per IEC 61000 4 5 Conducted RF Immunity CRFI per IEC 61000 4 6 Emissions per EN61000 6 4 Enclosure Port per CISPR 16 Low Voltage AC Mains Port per CISPR 16 Note This is a Class A product Vibration and Shock Standard The ACPS3320 is designed to pass the following Vibration and Shock standards Vibration Sinusoidal Operating Designed to comply with IEC 60068 2 6 10 500Hz ...

Page 25: ...ntents are lost when power is removed Yes No Non Volatile Memory Does this product contain Non Volatile memory i e Memory of whose contents is retained when power is removed Yes No Type EEPROM FLASH etc Size User Modifiable Function Process to Sanitize FLASH 1 Mbit Yes PCIe switch configuration Overwrite FLASH contents Acromag Representative Name Russ Nieves Title Director of Sales and Marketing E...

Page 26: ...on the front panel for easy identification Cables and termination panels or user defined terminations can be quickly mated to the field I O connectors Pin assignments are defined by the installed AcroPack module Refer to Figure 4 for a block diagram Figure 4 ACPS3320 RTM Block Diagram 7 1 Ordering Information Model Operating Temperature Range ACPS3320 RTM 40 to 85 C SIGNAL INTERFACE PRODUCTS Cable...

Page 27: ... Site A Field I O 33 Site A Field I O 34 GND 04 GND Site A Field I O 25 Site A Field I O 26 05 Site A Field I O 17 Site A Field I O 18 GND 06 GND Site A Field I O 9 Site A Field I O 10 D E F 01 Site A Field I O 47 Site A Field I O 48 GND 02 GND Site A Field I O 39 Site A Field I O 40 03 Site A Field I O 31 Site A Field I O 32 GND 04 GND Site A Field I O 23 Site A Field I O 24 05 Site A Field I O 1...

Page 28: ...eld I O 10 GND 08 GND Site B Field I O 1 Site B Field I O 2 D E F 01 N C 1 N C 1 GND 02 GND N C 1 N C 1 03 Site B Field I O 43 Site B Field I O 44 GND 04 GND Site B Field I O 35 Site B Field I O 36 05 Site B Field I O 27 Site B Field I O 28 GND 06 GND Site B Field I O 19 Site B Field I O 20 07 Site B Field I O 11 Site B Field I O 12 GND 08 GND Site B Field I O 3 Site B Field I O 4 G H I 01 N C 1 N...

Page 29: ... on the front panel of the ACPS3320 RTM The pinout is as follows in the table below J1 and Termination Panel AcroPack Field I O Signal 1 Field I O 1 35 Field I O 2 Reserved isolation Reserved isolation 2 Field I O 3 36 Field I O 4 Reserved isolation Reserved isolation 3 Field I O 5 37 Field I O 6 Reserved isolation Reserved isolation 4 Field I O 7 38 Field I O 8 Reserved isolation Reserved isolati...

Page 30: ...10 Field I O 19 44 Field I O 20 Reserved isolation Reserved isolation 11 Field I O 21 45 Field I O 22 Reserved isolation Reserved isolation 12 Field I O 23 46 Field I O 24 Reserved isolation Reserved isolation 13 Field I O 25 47 Field I O 26 Reserved isolation Reserved isolation 14 Field I O 27 48 Field I O 28 Reserved isolation Reserved isolation 15 Field I O 29 49 Field I O 30 Reserved isolation...

Page 31: ... 19 Field I O 37 53 Field I O 38 Reserved isolation Reserved isolation 20 Field I O 39 54 Field I O 40 Reserved isolation Reserved isolation 21 Field I O 41 55 Field I O 42 Reserved isolation Reserved isolation 22 Field I O 43 56 Field I O 44 Reserved isolation Reserved isolation 23 Field I O 45 57 Field I O 46 Reserved isolation Reserved isolation 24 Field I O 47 58 Field I O 48 Reserved isolatio...

Page 32: ...eld Immunity RFI per IEC 61000 4 3 Electrical Fast Transient Immunity EFT per IEC 61000 4 4 Surge Immunity per IEC 61000 4 5 Conducted RF Immunity CRFI per IEC 61000 4 6 Emissions per EN61000 6 4 Enclosure Port per CISPR 16 Low Voltage AC Mains Port per CISPR 16 Note This is a Class A product Vibration and Shock Standard The ACPS3320 RTM is designed to pass the following Vibration and Shock standa...

Page 33: ...AcroPack Series ACPS3320 CompactPCI Serial Carrier Board 33 Temperature MTBF Hours MTBF Years Failure Rate FIT1 40 C 54 011 721 6 165 7 18 51 1 FIT is Failures in 109 hours ...

Page 34: ...e Memory Does this product contain Volatile memory i e Memory of whose contents are lost when power is removed Yes No Non Volatile Memory Does this product contain Non Volatile memory i e Memory of whose contents is retained when power is removed Yes No Acromag Representative Name Russ Nieves Title Director of Sales and Marketing Email rnieves acromag com Office Phone 248 295 0838 Office Fax 248 6...

Page 35: ...ctPCI Serial Carrier Board 35 8 REVISION HISTORY The following table shows the revision history for this document Release Date Version EGR DOC Description of Revision 26 JUL 2018 ENZ Preliminary release 23 APR 2019 A ENZ ARP Release ...

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