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Receiver

Table 4-6: Receiver Signals

Signal

Width

Direction

Description

Clocks and Resets

pll_ref_clk

Input

Transceiver reference clock signal.

rxlink_clk

Input

RX link clock signal used by the Avalon-ST

interface. This clock is equal to RX data rate

divided by 40.
For Subclass 1, you cannot use the output of

rxphy_clk

signal as

rxlink_clk

signal. To sample

SYSREF

correctly, the core PLL must provide the

rxlink_clk

signal and must be configured as

normal operating mode.

rxlink_rst_n_reset_n

Input

Reset for the RX link clock signal. This reset is an

active low signal.

rxphy_clk[]

Output

Recovered clock signal. This clock is derived from

the clock data recovery (CDR) and the frequency

depends on the JESD204B IP core data rate.

rx_digitalreset[]

(25)

Input

Reset for the transceiver PCS block. This reset is an

active high signal.

rx_analogreset[]

(25)

Input

Reset for the CDR and transceiver PMA block.

This reset is an active high signal.

rx_islockedtodata[]

(25)

Output

This signal is asserted to indicate that the RX CDR

PLL is locked to the RX data and the RX CDR has

changed from LTR to LTD mode.

rx_cal_busy[]

(25)

Output

RX calibration in progress signal. This signal is

asserted to indicate that the RX transceiver calibra‐

tion is in progress.

Signal

Width

Direction

Description

Transceiver Interface

rx_serial_data[]

Input

Differential high speed serial input data. The clock

is recovered from the serial data stream.

(25)

The Transceiver PHY Reset Controller IP Core controls this signal.

4-36

Receiver

UG-01142

2015.05.04

Altera Corporation

JESD204B IP Core Functional Description

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Содержание JESD204B IP CORE

Страница 1: ...JESD204B IP Core User Guide Last updated for Altera Complete Design Suite 15 0 Subscribe Send Feedback UG 01142 2015 05 04 101 Innovation Drive San Jose CA 95134 www altera com ...

Страница 2: ... 3 7 Generating and Simulating the IP Core Testbench 3 8 Compiling the JESD204B IP Core Design 3 10 Programming an FPGA Device 3 11 JESD204B IP Core Design Considerations 3 11 Integrating the JESD204B IP core in Qsys 3 11 Pin Assignments 3 12 Adding External Transceiver PLL 3 13 Timing Constraints For Input Clocks 3 13 JESD204B IP Core Parameters 3 16 JESD204B IP Core Component Files 3 21 JESD204B...

Страница 3: ...e Dynamic Reconfiguration 5 49 Generating and Simulating the Design Example 5 55 Generating the Design Example For Compilation 5 56 Compiling the JESD204B IP Core Design Example 5 57 JESD204B IP Core Deterministic Latency Implementation Guidelines 6 1 Constraining Incoming SYSREF Signal 6 1 Programmable RBD Offset 6 2 Programmable LMFC Offset 6 5 JESD204B IP Core Debug Guidelines 7 1 Clocking Sche...

Страница 4: ...2 Uses SYNC_N detection to support determin istic latency 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respec...

Страница 5: ... Broadcast equipment Military equipment Medical equipment Test and measurement equipment Device Family Support Cyclone V FPGA device families Arria V FPGA device families Arria V GZ FPGA device families Arria 10 FPGA device families Stratix V FPGA device families Refer to the device support table andWhat s New in Altera IP page of the Altera website for detailed information Design Tools Qsys param...

Страница 6: ... design example component where you can customize the design for different converter devices 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service mar...

Страница 7: ...ice Synchronization throughSubclass1 orSubclass2 Logic Device TX Device Clock 2 Logic Device RX Device Clock 2 JESD204B TX IP Core JESD204B RX IP Core Key features of the JESD204B IP core Data rate of up to 12 5 Gbps Run time JESD204B parameter configuration L M F S N K CS CF MAC and PHY partitioning for portability Subclass 0 mode for backward compatibility to JESD204A Subclass 1 mode for determi...

Страница 8: ... to use the Quartus II software to merge the transceivers and group them into the transceiver architecture For example to create two instances of the JESD204B TX IP core with four lanes each and four instances of the JESD204 RX IP core with two lanes each you can apply one of the following options MAC and PHY option 1 Generate JESD204B TX IP core with four lanes and JESD204B RX IP core with two la...

Страница 9: ... during parameterization which means that run time programmability can only fall back from the parameterized and generated hardware but not beyond the parameterized IP core You can use run time configuration for prototyping or evaluating the performance of converter devices with various LMF configurations However in actual production Altera recommends that you generate the JESD204B IP core with th...

Страница 10: ...t the channels are on the same side In MAC and PHY integrated mode you can generate up to 8 channels In bonded channel configuration the lower transceiver clock skew and equal latency in the transmitter phase compensation FIFO for all channels result in a lower channel to channel skew You must use adjacent channels when you select 6 bonding You must also place logical channel 0 in either physical ...

Страница 11: ...0 to 12 0 2 0 to 12 5 312 50 Arria 10 2 2 2 0 to 9 83 2 0 to 12 5 312 50 Arria 10 3 1 2 0 to 12 0 2 0 to 12 5 312 50 Arria 10 3 2 2 0 to 9 83 2 0 to 12 5 Arria 10 4 3 2 0 to 8 83 2 0 to 12 5 312 50 Arria 10 5 3 2 0 to 8 0 2 0 to 8 0 312 50 Stratix V 1 1 or 2 2 0 to 12 2 2 0 to 12 5 312 50 Stratix V 2 1 or 2 2 0 to 12 2 2 0 to 12 5 312 50 Stratix V 2 3 2 0 to 9 8 2 0 to 12 5 5 312 50 3 Select Enabl...

Страница 12: ...ter Setting JESD204B Wrapper Base and PHY JESD204B Subclass 1 Data Rate 5 Gbps PCS Option Enabled Hard PCS PLL Type ATX for 10 series devices CMU for V series devices Bonding Mode Non bonded Reference Clock Frequency 125 0 MHz Octets per frame F 1 Enable Scrambler SCR Off Enable Error Code Correction ECC_EN Off 3 Select Enable Soft PCS to achieve maximum data rate For the TX IP core enabling soft ...

Страница 13: ...e V RX 1 1047 1543 1200 1 2 1594 2325 1825 2 4 2832 4043 3080 4 8 5354 7525 5585 8 TX 1 728 1148 948 0 2 889 1424 1066 0 4 1218 1941 1293 0 8 1715 2837 1757 0 Arria V RX 1 1052 1543 1197 1 2 1586 2325 1823 2 4 2830 4043 3077 4 8 5330 7525 5584 8 TX 1 719 1148 947 0 2 887 1424 1062 0 4 1208 1941 1292 0 8 1724 2853 1754 0 Arria V GZ RX 1 1062 1542 1215 0 2 1634 2363 1858 0 4 2934 4097 3141 0 8 5526 ...

Страница 14: ...n page 3 16 Fitter Resources Reports in the Quartus II Help Information about the Quartus II resource utilization reporting including ALMs needed 6 M10K for Arria V device M20K for Arria V GZ Stratix V and Arria 10 devices 7 The Quartus II software may auto fit to use MLAB when the memory size is too small Conversion from MLAB to M20K or M10K was performed for the numbers listed above 7 The Quartu...

Страница 15: ... replace the MegaWizard Plug In Manager for IP selection and parameterization beginning in Quartus II software version 14 0 Use the IP Catalog and parameter editor to locate and paramaterize Altera and other supported IP cores Related Information IP User Guide Documentation Altera IP Release Notes 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS a...

Страница 16: ...I software Click Project Upgrade IP Components to identify and upgrade outdated IP core variants Icons in the Upgrade IP Components dialog box indicate when IP upgrade is required optional or unsupported for IP cores in your design This dialog box may open automatically when you open a project containing upgradeable IP variations You must upgrade IP cores that require upgrade before you can compil...

Страница 17: ...fer to the Description for details about IP core version differences IP Upgrade Unspported Upgrade of the IP variation is not supported in the current version of the Quartus II software due to incompatibility with the current version of the Quartus II software You are prompted to replace the unsupported IP core with a supported equivalent IP core from the IP Catalog Refer to the Descrip tion for d...

Страница 18: ...e The parameter editor opens allowing you to adjust parameters and regenerate the latest version of the IP core Figure 3 2 Upgrading IP Cores Runs AutoUpgrade onallsupportedoutdatedcores OpenseditorformanualIPupgrade AutoUpgrade supported Upgraderequired Upgrade optional Upgradedetails AutoUpgrade successful Note IP cores older than Quartus II software version 12 0 do not support upgrade Altera ve...

Страница 19: ...rompts you to specify an IP variation name optional ports and output file generation options The parameter editor generates a top level Qsys system file qsys or Quartus II IP file qip representing the IP core in your project You can also parameterize an IP variation without an open project Use the following features to help you quickly locate and select an IP core Filter IP Catalog to Show IP for ...

Страница 20: ...For more information about using the Qsys IP Catalog refer to Creating a System with Qsys in the Quartus II Handbook Design Walkthrough This walkthrough explains how to create a JESD204B IP core design using Qsys in the Quartus II software After you generate a custom variation of the JESD204B IP core you can incorporate it into your overall project Creating a New Quartus II Project You can create ...

Страница 21: ... to complete the Quartus II project creation Parameterizing and Generating the IP Core Before you begin Refer to Table 3 6 for the IP core parameter values and description 1 In the IP Catalog Tools IP Catalog locate and double click the name of the IP core you want to customize 2 Specify a top level name for your custom IP variation This name identifies the IP core variation files in your project ...

Страница 22: ...ick Finish or Generate HDL to generate synthesis and other optional files matching your IP variation specifications The parameter editor generates the top level qip or qsys IP variation file and HDL files for synthesis and simulation The top level IP variation is added to the current Quartus II project Click Project Add Remove Files in Project to manually add a qip or qsys file to a project Make a...

Страница 23: ...HDL to generate the simulation files Simulating the IP Core Testbench The JESD204B IP core simulation supports the following simulators ModelSim Altera SE AE VCS VCS MX Cadence Aldec Riviera Note VHDL is not supported in ModelSim Altera AE VCS simulators and Aldec Riviera for Arria 10 devices only Table 3 2 Simulation Setup Scripts This table lists the simulation setup scripts and run scripts Simu...

Страница 24: ...pass fail indication on completion To simulate the testbench design using the VCS VCS MX in Linux or Cadence simulator follow these steps 1 Launch the VCS VCS MX or Cadence simulator 2 On the File menu click Change Directory Select example_design_directory ip_sim testbench simulator name 3 Run the run_altera_jes204_tb sh file This file compiles the design and runs the simulation automati cally pro...

Страница 25: ...rd interfaces like clock reset Avalon MM Avalon ST HSSI bonded clock HSSI serial clock and interrupt interfaces within Qsys However for conduit interfaces you are advised to export all those interfaces and handle them outside of Qsys 9 This is because conduit interfaces are not part of the standard interfaces Thus there is no guarantee on compatibility between different conduit interfaces Note The...

Страница 26: ...itter tool You must also specify the signals that should be assigned to device I O pins You can create virtual pins to avoid making specific pin assignments for top level signals This is useful when you want to perform compilation but are not ready to map the design to hardware Altera recommends that you create virtual pins for all unused top level signals to improve timing closure Note Do not cre...

Страница 27: ... paths are not yet known Therefore the Quartus II software cannot incorporate the final signal names in the sdc file that it automatically generates Instead you must manually modify the clock signal names in this file to integrate these constraints with the timing constraints for your full design This section describes how to integrate the timing constraints that the Quartus II software generates ...

Страница 28: ..._groups command After you complete your design you must modify the clock names in your sdc file to the full design clock names taking into account both the IP core instance name in the full design and the design hierarchy Be careful when adding the timing exceptions based on your design for example when the JESD204B IP core handles asynchronous timing between the txlink_clk rxlink_clk pll_ref_clk ...

Страница 29: ...vice_clk base and generated clock names as reported by report_clock commands group jesd204_avs_clk group phy_mgmt_clk base and generated clock names as reported by report_clock commands rx_pll_ref_clk txlink_clk device_clk 125 rxlink_clk tx_avs_clk jesd204_avs_clk 100 rx_avs_clk reconfig_clk 10 phy_mgmt_clk 75 However if your design requires you to connect the rx_avs_clk and reconfig_clk to the sa...

Страница 30: ... report_clock commands rx_pll_ref_clk txlink_clk rxlink_clk tx_avs_clk mgmt_clk 100 rx_avs_clk reconfig_clk 11 JESD204B IP Core Parameters Table 3 6 JESD204B IP Core Parameters Parameter Value Description Main Tab Device Family Arria V Arria V GZ Arria 10 Cyclone V Stratix V Select the targeted device family JESD204B Wrapper Base Only PHY Only Both Base and PHY Select the JESD204B wrapper Base Onl...

Страница 31: ... Soft PCS Select the PCS modes Enabled Hard PCS utilize Hard PCS components Select this option to minimize resource utilization with data rate that supports up to the limitation of the Hard PCS Note For this setting you will utilize 8G PCS mode with 20 bits PMA width and 32 bits PCS width Enabled Soft PCS utilize Soft PCS components Select this option to allow higher supported data rate but increa...

Страница 32: ...ls Enable Altera Debug Master Endpoint 14 On Off Turn on this option for the Transceiver Native PHY IP core to include an embedded Altera Debug Master Endpoint ADME This ADME connects internally to the Avalon MM slave interface of the Transceiver Native PHY and can access the reconfiguration space of the transceiver It can perform certain test and debug functions via JTAG using System Console This...

Страница 33: ...l mode and enable this parameter to be configurable Otherwise the parameter F is in derived mode You have to enable this parameter and configure the appropriate F value if the transport layer in your design is supporting Control Word CF and or High Density format HD Note The auto derived F value using formula F M S N 8 L may not apply if parameter CF and or parameter HD are enabled Octets per fram...

Страница 34: ...oss the lane boundary Enable Error Code Correction ECC_EN On Off Turn on this option to enable error code correction ECC for memory blocks Phase adjustment request PHADJ On Off Turn on this option to specify the phase adjustment request to the DAC On Request for phase adjustment Off No phase adjustment This parameter is valid for Subclass 2 mode only Adjustment resolution step count ADJCNT 0 15 Se...

Страница 35: ...in Quartus II software variation name sip Contains IP core library mapping information required by the Quartus II software The Quartus II software generates a sip file during generation of some Altera IP cores You must add any generated sip file to your project for use by NativeLink simulation and the Quartus II Archiver variation name spd Contains a list of required simulation files for your IP c...

Страница 36: ...D204B IP Core Testbench Block Diagram The external ATX PLL is present only in the JESD204B IP core testbench targeting an Arria 10 FPGA device family Reference Clock Generator Link Clock Generator AVS Clock Generator Packet Generator Packet Checker ATX PLL Transceiver PHY Reset Controller IP Core JESD204B IP Core Duplex Loopback JESD204B Testbench Related Information Generating and Simulating the ...

Страница 37: ... next positive edge of the link_clk signal the JESD204B RX link powers up by releasing its reset signal 6 Once the link is out of reset a SYSREF pulse is generated to reset the LMFC counter inside both the JESD204B TX and RX IP core 7 When the txlink_ready signal is asserted the packet generator starts sending packets to the TX datapath 8 The packet checker starts comparing the packet sent from th...

Страница 38: ...hare the clock and reset if the link rates are the same 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respecti...

Страница 39: ...Layer Transport Layer Data Link Layer Physical Layer Word Aligner Soft Logic Hard Logic JESD204B IP Core JESD204B Design Example jesd204_tx_top MAC jesd204_tx_base MAC jesd204_rx_base PHY jesd204_rx_phy PHY jesd204_tx_phy jesd204_rx_top 8B 10B Encoder 8B 10B Decoder SYNC SYNC Frame Lane Alignment Character Buffer Replace Monitor 4 2 JESD204B IP Core Functional Description UG 01142 2015 05 04 Alter...

Страница 40: ...nnel Serial Interface RX_n RX_p 32 Bits Architecture The JESD204B IP core consist of 32 bit internal datapath per lane This means that JESD204B IP Core expects the data samples to be assembled into 32 bit data 4 octets per lane in the transport layer before sending the data to the Avalon ST data bus The JESD204 IP core operates in the link clock domain The link clock runs at data rate 40 because i...

Страница 41: ...transmitter block which interfaces to DAC devices takes one of more digital sample streams and converts them into one or more serial streams The transmitter performs the following functions Data scrambling Frame or lane alignment Character generation Serial lane monitoring 8B 10B encoding Data serializer Figure 4 3 Transmitter Data Path Block Diagram TX Frame Deassembly Per Device TX CSR Per Devic...

Страница 42: ...rs deactivate the SYNC_N signal the JESD204 TX IP core continues to transmit K symbols until the next LMFC boundary At the next LMFC boundary the JESD204B IP core transmits ILAS data sequence There is no programmability to use a later LMFC boundary TX ILAS When lane alignment sequence is enabled through the csr_lane_sync_en register the ILAS sequence is transmitted after the CGS phase The ILAS pha...

Страница 43: ...k 4 F 7 0 F Number of octets per frame per lane 5 0 0 0 K 4 0 K Number of frames per multi frame 6 M 7 0 M Number of converters per device 7 CS 1 0 0 N 4 0 CS Number of control bits per sample N Converter resolution 8 SUBCLASSV 2 0 N_PRIME 4 0 SUBCLASSV Subclass version N_PRIME Total bits per sample 9 JESDV 2 0 S 4 0 JESDV JESD204 version S Number of samples per converter per frame 10 HD 0 0 CF 4 ...

Страница 44: ... K28 3 marks the end of multi frame with dummy data in between The dummy data is an increment of Dx y User Data Phase During the user data phase character replacement at the end of frame and end of multi frame is opportunistically inserted so that there is no additional overhead for data bandwidth Character replacement for non scrambled data The character replacement for non scrambled mode in the ...

Страница 45: ...e 8B 10B encoding has sufficient bit transition density 3 8 transitions per 10 bit symbol to allow clock recovery by the receiver The control characters in this scheme allow the receiver to synchronize to 10 bit boundary insert special character to mark the start and end of frames and start and end of multi frames detect single bit errors The JESD204 IP core supports transmission order from MSB fi...

Страница 46: ...e done in the TX link so that the RX link can execute frame and lane alignment monitoring based on the JESD204B specification RX CGS The CGS phase is the link up phase that monitors the detection of K28 5 character The CGS phase is achieved through the following process Once the word boundary is aligned the RX PHY layer detects the K28 5 20 bit boundary and indicate that the character is valid The...

Страница 47: ...ment detection process If two successive valid alignment characters are detected in the same position other than the assumed end of frame without receiving a valid or invalid alignment character at the expected position between two alignment characters the receiver realigns its frame to the new position of the received alignment characters If lane realignment can result in frame alignment error th...

Страница 48: ...ne it is trying to read from Then proceed to read from the csr_ilas_octet register Initial Lane Synchronization The receivers in Subclass 1 and Subclass 2 modes store data in a memory buffer Subclass 0 mode does not store data in the buffer but immediately releases them on the frame boundary as soon as the latest lane arrives The RX IP core detects the start of multi frame of user data per lane an...

Страница 49: ...6CharacterElasticBufferDelayforLatestArrival DeterministicDelay fromTXILAOutput toRXILAOutput RX PHY Layer The word aligner block identifies the MSB and LSB boundaries of the 10 bit character from the serial bit stream Manual alignment is set because the K character must be detected in either LSB first or MSB first mode When the programmed word alignment pattern is detected in the current word bou...

Страница 50: ...re the ADC groups share both the device clock and SYSREF 18 75 MHz and 9 375 MHz provide one SYSREF running at 9 375 MHz and device clock for all the ADC and DAC groups because the SYSREF period in the DAC is a multiplication of n integer Group Configuration SYSREF Frequency ADC Group 1 2 ADCs LMF 222 K 16 Data rate 6 Gbps 6 GHz 40 2 x 16 4 18 75 MHz ADC Group 2 2 ADCs LMF 811 K 32 Data rate 6 Gbp...

Страница 51: ...this option applies to all lanes Mixed mode operation where scrambling is enabled for some lanes is not permitted The scrambling polynomial 1 x14 x15 The descrambler can self synchronize in eight octets In a typical application where the reset value of the scrambler seed is different from the converter device to FPGA logic device the correct user data is recovered in the receiver in two link clock...

Страница 52: ...unctional link will still operate You must manage the trace length for the SYSREF signal and also the differential pair to minimize skew The SYNC_N is the direct signal from the DAC converters The error signaling from SYNC_N is filtered and sent out as dev_sync_n output signal The dev_sync_n signal from the JESD204B TX IP core must loopback into the mdev_sync_n signal of the same instance without ...

Страница 53: ...Device 1 L Converter Device 2 L SYNC_N SYNC_N SYNC_N Clock Chip and SYSREF FPGA Reference Clock SYSREF DAC Reference Clock SYSREF JESD204B IP Core TX JESD204B IP Core TX JESD204B IP Core TX Related Information Programmable RBD Offset on page 6 2 Link Reinitialization The JESD204B TX and RX IP core support link reinitialization 4 16 Link Reinitialization UG 01142 2015 05 04 Altera Corporation JESD2...

Страница 54: ...ctions describe the detailed operation for each subclass mode TX Subclass 0 Upon reset deassertion the JESD204B TX IP core is in CGS phase SYNC_N deassertion from the converter device enables the JESD204B TX IP core to exit CGS phase and enter ILAS phase if csr_lane_sync_en 1 or User Data phase if csr_lane_sync_en 0 TX Subclass 1 Upon reset deassertion the JESD204B TX IP core is in CGS phase SYNC_...

Страница 55: ...r reporting through SYNC_N when SYNC_N is asserted for two frame clock periods if F 2 or four frame clock periods if F 1 When the downstream device reports an error through SYNC_N the TX IP core issues an interrupt The TX IP core samples the SYNC_N pulse width using the link clock For a special case of F 1 two frame clock periods are less than one link clock Therefore the error signaling from the ...

Страница 56: ...he link clock and frame clock to be synchronous For more information refer to the F1 F2_FRAMECLK_DIV parameter description and its relationship to the frame clock TX RX Transceiver Serial Clock and Parallel Clock Internally derived from the data rate during IP core generation The serial clock is the bit clock to stream out serialized data The transceiver PLL supplies this clock and is internal to ...

Страница 57: ...e device clock is used as the transceiver PLL reference clock and also the core PLL reference clock The available frequency depends on the PLL type bonding option number of lanes and device family During IP core generation the Quartus II software recommends the available device clock frequency for the transceiver PLL based on the user selection Note You need to generate the Altera PLL IP core in A...

Страница 58: ...me clock and AVS clock The link clock and frame clock must be synchronous Related Information Clock Correlation on page 4 23 Link Clock The device clock is the timing reference for the JESD204B system Due to the clock network architecture in the FPGA JESD204 IP core does not use the device clock to clock the SYSREF signal because the GCLK or RCLK is not fully compensated You are recommended to use...

Страница 59: ...he Altera PLL IP core that provides the link clock must to be in normal mode to phase compensate the link clock to the device clock Based on hardware testing to get a fixed latency at least 32 octets are recommended in an LMFC period so that there is a margin to tune the RBD release opportunity to compensate any lane to lane deskew across multiple resets If F 1 then K 32 would be optimal as it pro...

Страница 60: ...clock counter F K 4 4 8 4 8 link clocks 18 Example 3 Targeted device with LMF 421 K 32 and Data rate 10 0 Gbps Device Clock selected 250 MHz obtained during IP core generation Link Clock 10 GHz 40 250 MHz Frame Clock 10 GHz 10 1 1 GHz 20 Local Multi frame clock 1 GHz 32 31 25 MHz SYSREF Frequency Local Multi frame Clock n n integer 1 2 Local multi frame clock counter F K 4 1 32 4 8 link clocks 18 ...

Страница 61: ... in reset Deassert the txlink_rst_n and txframe_ rst_n signals after the Altera PLL IP core is locked and the tx_ready signal from the Transceiver Reset Controller is asserted Deassert the rxlink_rst_n and rxframe_ rst_n signals after the Transceiver CDR rx_islockedtodata signal and rx_ ready signal from the Transceiver Reset Controller are asserted The txlink_rst_n rxlink_rst_n and txframe_rst_n ...

Страница 62: ...s_rst_n TX RX AVS CSR Clock Active low reset controlled by the clock and reset unit Typically both signals can be deasserted after the core PLL and transceiver PLL are locked and out of reset If you want to dynamically modify the LMF at run time you can program the CSRs after AVS reset is deasserted This phase is referred to as the configuration phase After the configuration phase is complete then...

Страница 63: ... program the JESD204B IP core if the default IP core register settings need to change 5 Deassert both the link reset for the IP core and the frame reset for the transport layer Figure 4 9 Reset Sequence Timing Diagram pll_ref_clk tx rx pll GENERIC STATES TRANSCEIVER PLL POWERUP JESD204B IP OPERATION pll_locked from TX PLL txlink_clk rxlink_clk txlink_rst_n rxlink_rst_n txframe_clk rxframe_clk txfr...

Страница 64: ...must provide the txlink_clk signal and must be configured as normal operating mode txlink_rst_n_reset_n 1 Input Reset for the TX link clock signal This reset is an active low signal txphy_clk L Output TX parallel clock output for the TX PCS This clock must have the same frequency as txlink_clk signal This clock is output as an optional port for user if the txlink_clk and txframe_clk signals are op...

Страница 65: ...ing_clocks Single Channel tx_bonding_clocks_ ch 0 L 1 Multiple Channels 6 Input The transceiver PLL bonding clocks The transceiver PLL generation provides these clocks This signal is only available if you select Bonded mode for Arria 10 FPGA variants tx_serial_clk0 Single Channel tx_serial_clk0_ ch 0 L 1 Multiple Channels 1 Input The transceiver PLL serial clock This is the serializer clock in the...

Страница 66: ...eries FPGA variants You must connect these signals to the Transceiver Reconfiguration Controller IP core regardless of whether run time reconfigu ration is enabled or disabled The Transceiver Reconfiguration Controller IP core also supports various calibration function during transceiver power up reconfig_clk 1 Input The Avalon MM clock input The frequency range is 100 125 MHz This signal is only ...

Страница 67: ...reconfiguration for Arria 10 FPGA variants reconfig_avmm_ waitrequest 1 Output Wait request signal This signal is only available if you enable dynamic reconfiguration for Arria 10 FPGA variants Signal Width Direction Description Avalon ST Interface jesd204_tx_link_ data L 32 Input Indicates a 32 bit user data at txlink_clk clock rate where four octets are packed into a 32 bit data width per lane T...

Страница 68: ...ept data The Avalon ST sink interface asserts this signal on the JESD204B link state of ILAS 4th multiframe and also the USER_DATA phase The ready latency is 0 Signal Width Direction Description Avalon MM Interface jesd204_tx_avs_clk 1 Input The Avalon MM interface clock signal This clock is asynchronous to all the functional clocks in the JESD204B IP core The JESD204B IP core can handle any cross...

Страница 69: ... jesd204_tx_avs_read 1 Input This signal is asserted to indicate a read transfer This is an active high signal and requires the jesd204_tx_avs_ readdata 31 0 signal to be in use jesd204_tx_avs_write 1 Input This signal is asserted to indicate a write transfer This is an active high signal and requires the jesd204_tx_avs_ writedata 31 0 signal to be in use jesd204_tx_avs_ readdata 32 Output 32 bit ...

Страница 70: ...of this signal This signal is also asserted during software initiated synchronization mdev_sync_n 1 Input Indicates a multidevice synchronization request Synchronize signal combination should be done externally and then input to the JESD204B IP core through this signal For subclass 0 combine the dev_sync_n signal from all multipoint links before connecting to the mdev_sync_n signal For subclass 1 ...

Страница 71: ...verter resolution The transport layer can use this signal as a run time parameter csr_np 5 Output Indicates the total number of bits per sample The transport layer can use this signal as a run time parameter csr_s 5 Output Indicates the number of samples per converter per frame cycle The transport layer can use this signal as a run time parameter csr_hd 1 Output Indicates the high density data for...

Страница 72: ...and OOB jesd204_tx_int 1 Output Interrupt pin for the JESD204B IP core Interrupt is asserted when any error or synchronization request is detected Configure the tx_err_enable register to set the type of error that can trigger an interrupt Signal Width Direction Description Debug or Testing jesd204_tx_dlb_ data L 32 Output Optional signal for parallel data from the DLL in TX to RX loopback testing ...

Страница 73: ... on the JESD204B IP core data rate rx_digitalreset 25 L Input Reset for the transceiver PCS block This reset is an active high signal rx_analogreset 25 L Input Reset for the CDR and transceiver PMA block This reset is an active high signal rx_islockedtodata 25 L Output This signal is asserted to indicate that the RX CDR PLL is locked to the RX data and the RX CDR has changed from LTR to LTD mode r...

Страница 74: ...isabled The Transceiver Reconfiguration Controller IP core also supports various calibra tion function during transceiver power up reconfig_clk 1 Input The Avalon MM clock input The frequency range is 100 125 MHz This signal is only available if you enable dynamic reconfiguration for Arria 10 FPGA variants reconfig_reset 1 Input Reset signal for the Transceiver Reconfiguration Controller IP core T...

Страница 75: ...ut Indicates a 32 bit data from the DLL to the transport layer The data format is big endian where the earliest octet is placed in bit 31 24 and the latest octet is placed in bit 7 0 jesd204_rx_link_valid 1 Output Indicates whether the data to the transport layer is valid or invalid The Avalon ST source interface in the RX core cannot be backpressured and will transmit the data when the jesd204_rx...

Страница 76: ...tie this port to 1 jesd204_rx_avs_ address 8 Input For Avalon MM slave the interconnect translates the byte address into a word address in the address space so that each slave access is for a word of data For example address 0 selects the first word of the slave and address 1 selects the second word of the slave jesd204_rx_avs_ writedata 32 Input 32 bit data for write transfers The width of this s...

Страница 77: ... of reporting the link error through this signal the JESD204B IP core uses the jesd204_rx_int signal to interrupt the CPU sof 4 Output Indicates a start of frame 3 start of frame for jesd204_rx_link_ data 31 24 2 start of frame for jesd204_rx_link_ data 23 16 1 start of frame for jesd204_rx_link_ data 15 8 0 start of frame for jesd204_rx_link_ data 7 0 somf 4 Output Indicates a start of multiframe...

Страница 78: ... a run time parameter csr_m 8 Output Indicates the number of converters for the link The transport layer can use this signal as a run time parameter csr_cs 2 Output Indicates the number of control bits per sample The transport layer can use this signal as a run time parameter csr_n 5 Output Indicates the converter resolution The transport layer can use this signal as a run time parameter csr_np 5 ...

Страница 79: ...Interrupt is asserted when any error is detected Configure the rx_err_enable register to set the type of error that can trigger an interrupt Signal Width Direction Description Debug or Testing jesd204_rx_dlb_data L 32 Input Optional signal for parallel data to the DLL in TX to RX loopback testing 26 jesd204_rx_dlb_data_ valid L Input Optional signal to indicate valid data for each byte in TX to RX...

Страница 80: ... the IP core s Avalon MM slave In this connection the Avalon MM master address bit 2 connects to the IP core Avalon MM slave address bit 0 while the Avalon MM master bit 9 connects to the IP core address bit 7 TX register map RX register map Register Access Type Convention This table describes the register access type for Altera IP cores Table 4 7 Register Access Type and Definition Access Type De...

Страница 81: ...ve no effect Software writes 1 shall set the bit to 1 Hardware clears the bit to 0 if the bit has been set to 1 by software Software set has higher priority than hardware clear 4 44 Register Access Type Convention UG 01142 2015 05 04 Altera Corporation JESD204B IP Core Functional Description Send Feedback ...

Страница 82: ...RION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to curr...

Страница 83: ...the design example architecture with reference to the note numbers in the design example block diagram 1 For multiple links the JESD204B IP core is instantiated multiple times For example in 2x112 LMF configuration two cores are instantiated where each core is configured at LMF 112 27 2 The number of pattern generator or pattern checker instances is equivalent to the parameter value of LINK The da...

Страница 84: ...orresponds to a separate external converter per device or clock chip For example in a system that interacts with both DAC and ADC two MIFs are needed one each for DAC and ADC 11 The PLL reconfiguration and transceiver reconfiguration controller instances are only required for run time reconfiguration of the data rate Design Example Components The design example for the JESD204B IP core consists of...

Страница 85: ...onfiguration Operation Operation Avalon MM Interface Signal Byte Address Offset 6bits Bit Value Arria V and Stratix V Devices Set MIF base address pll_mgmt_ 0x01F 8 0 0x000 maximum configuration or 0x02E downscale configuration Write to the START register to begin pll_mgmt_ 0x02 0 0 0x01 Arria 10 Devices Start MIF streaming with MIF base address specified in data value pll_mgmt_ 0x010 31 0 0x000 m...

Страница 86: ... the control unit directly communicates with the transceiver in the JESD204B IP core through the reconfig_avmm_ interface signals The following transceiver reconfiguration controller Avalon MM operations are involved during data rate reconfiguration Table 5 2 Transceiver Reconfiguration Controller Operation for Arria V and Stratix V Devices Operation Avalon MM Interface Signal Byte Address Offset ...

Страница 87: ...ume 2 Transceivers More information about the device usage mode Pattern Generator The pattern generator instantiates any supported generators and has an output multiplexer to select which generated pattern to forward to the transport layer based on the test mode during run time Additionally the pattern generator also supports run time reconfiguration downscale on the number of converters per devic...

Страница 88: ... the number of converters per device M and samples per converter per frame S The pattern checker can be either a parallel PRBS checker alternate checkerboard checker or ramp wave checker The data input bus width of the pattern checker is equivalent to the value of FRAMECLK_DIV M S N The pattern checker includes an ERR_THRESHOLD parameter to control the number of error tolerance allowed in the chec...

Страница 89: ...RX path maps the descrambled octets from the DLL to a specific conversion sample format before streaming them to the AL through the Avalon ST interface reports AL error to the DLL if it encounters a specific error condition on the Avalon ST interface during RX data streaming Supported System Configuration The transport layer supports static configurations where before compilation you can modify th...

Страница 90: ...e from F 8 to F 4 and F 2 but not F 1 Relationship Between Frame Clock and Link Clock The frame clock and link clock are synchronous The ratio of link_clk period to frame_clk period is given by this formula 32 x L M x S x N Table 5 3 txframe_clk and rxframe_clk Frequency for Different F Parameter Settings For a given ftxlink txlink_clk frequency and frxlink rxlink_clk frequency the ftxframe txfram...

Страница 91: ...to Avalon ST Interface 0 2nd jesd204_rx_ctrlout 0 Transport Layer to Avalon ST Interface 0 1 2 3 4 5 6 7 8 9 10 11 2nd jesd204_rx_dataout 11 0 Transport Layer to Avalon ST Interface 1st jesd204_tx_datain 11 0 Avalon ST interface to Transport Layer 0 1 2 3 4 5 6 7 8 9 10 11 1st jesd204_rx_dataout 11 0 Transport Layer to Avalon ST Interface Bit Position TX to RX Channel jesd204_tx_link_datain 31 0 T...

Страница 92: ...ch depends on the F and L parameter bus_width M S N F M S N_PRIME 8 L M S 8 F L N_PRIME bus_width 8 F L N N_PRIME Tail bits padding block pads incoming data jesd204_tx_datain with 0 if N 16 so that the padded data is 16 bits per sample Assembling block arranges the resulting data bits in a specific way according to the mapping scheme refer to Figure 5 2 Multiplexing block sends the multiplexed dat...

Страница 93: ...utput bus width size The width depends on the CS parameter as well as the M and S parameters When CS is 0 the control data is one bit wide tie the signal to 0 If CS 0 the bus width 1 Otherwise the bus width OUTPUT_ BUS_WIDTH N CS while OUTPUT_BUS_WIDTH N M S OUTPUT_ BUS_ WIDTH N CS Table 5 5 Assembler Signals Signal Clock Domain Direction Description Control Unit txlink_clk Input TX link clock sig...

Страница 94: ...ed in the cases listed in TX Path Data Remapping section jesd204_tx_ controlin CONTROL_ BUS_WIDTH 1 0 txframe_clk Input TX control data from the Avalon ST source interface The source shall arrange the data in a specific order as illustrated in the cases listed in TX Path Data Remapping section jesd204_tx_data_ valid txframe_clk Input Indicates whether the data from the Avalon ST source interface t...

Страница 95: ...LL jesd204_tx_ link_valid input pin jesd204_tx_link_ early_ready 30 txlink_clk Input Indicates that the DLL requires valid data at the subsequent implementation specific duration Connect this signal to the TX DLL jesd204_tx_ frame_ready output pin jesd204_tx_link_ error txlink_clk Output Indicates an error at the Avalon ST source interface Specifically this signal is asserted when jesd204_tx_data_...

Страница 96: ... to be powered down To interleave the de commision channels you need to modify the interface connection from the DLL to transport layer Connect this signal to the TX DLL csr_l output pin csr_f 7 0 31 mgmt_clk Input Indicates the number of octets per frame This 8 bit bus represents the F value in zero based binary format For example if F 2 the csr_ f 7 0 00000001 This design example supports the fo...

Страница 97: ...d value beyond the supported range may result in undeterminable behavior in the transport layer You must ensure that the csr_n 4 0 value always match the system parameter N value Connect this signal to the TX DLL csr_n output pin TX Path Operation The data transfer protocol between the Avalon ST interface and the TX path transport layer is data transfer with backpressure where ready_latency 0 5 16...

Страница 98: ..._tx_link_early_ready jesd204_tx_data_ready jesd204_tx_datain 15 0 jesd204_tx_link_data_valid jesd204_tx_link_datain 31 0 junk All 0s d0 15 0 d1 15 0 d2 15 0 d3 15 0 d4 15 0 d5 15 0 d6 15 0 d7 15 0 d8 15 0 d9 15 0 d10 15 0 d0 15 0 d1 15 0 d2 15 0 d3 15 0 d4 15 0 d5 15 0 d6 15 0 d7 15 0 d8 15 0 d9 15 0 All 0s TX Data Transmission This section explains the data transmission behavior when there is a v...

Страница 99: ... txlink_clk txframe_rst_n txlink_rst_n jesd204_tx_datavalid jesd204_tx_link_early_ready jesd204_tx_datain 63 0 LINK jesd204_tx_link_ready jesd204_tx_link_datain 31 0 txframe_clk T0 T1 WhenF 8 thedatalatencyforjesd204_tx_link_datainshouldalways beinanevenlatencylink_clkcounttoensurethatthefirstvaliddatacaptured bytheTXlinkisT0datafollowedbyT1data TX Path Data Remapping The JESD204B IP core implemen...

Страница 100: ...a sample of S 1 of converter M 1 For example if S 4 and M 4 the most significant bits will be occupied by sample 3 of converter 3 3 In this example there is no control word because CF 0 Control bits are added if CS 1 Depending on the value of CS and N the number of tail bits added is N N CS For example N 16 N 12 and CS 2 the number of tail bits added to form a nibble group NG is 2 4 The JESD204B I...

Страница 101: ...mthe converterisNbitswide Theuserreordersthe datasothatM0S0is attheLSBandM M 1 S S 1 isatthe MSB Dataoutfrom theRXhastthesame orientation M0S0at theLSB Addthecontrolbit Addthetailbitto N 16 Thetransportlayer reshufflesthedatain bigendianformat F 8inthisexample 2ndlinkclock 1stlinkclock 32bitsofdataper laneinthelinkclock domainispackedto theJESD204BIPcore ThisRegionoftheTransportLayer IsintheFrameC...

Страница 102: ...S 2 M0S0 F3F7 M0S1 F11F15 Case2 M 2 S 1 M0S0 F3F7 M1S0 F11F15 F1_ FRAMCLK_ DIV 4 33 jesd204_tx_datain 127 0 F11F15 F3F7 F10F114 F2F6 F9F13 F1F5 F8F12 F0F4 Lane L3 L2 L1 L0 Data Out F12 F13 F14 F15 F8 F9 F10 F11 F4 F5 F6 F7 F0 F1 F2 F3 Table 5 7 Data Mapping for F 2 L 4 F 2 Supported M and S M S 4 for F 2 L 4 F 2 supports either case1 M 1 S 4 case2 M 2 S 2 or case3 M 4 S 1 32 The effective frame cl...

Страница 103: ...x_datain 127 0 F14F15 F10F11 F6F7 F2F3 F12F13 F8F9 F4F5 F0F1 Lane L3 L2 L1 L0 Data Out F12 F13 F14 F15 F8 F9 F10 F11 F4 F5 F6 F7 F0 F1 F2 F3 Table 5 8 Data Mapping for F 4 L 4 F 4 Supported M and S M S 8 for F 4 L 4 F 4 supports either case1 M 1 S 8 case2 M 2 S 4 case3 M 4 S 2 or case4 M 8 S 1 F 4 jesd204_tx_ datain 127 0 F14F15 F12F13 F10F11 F8F9 F6F7 F4F5 F2F3 F0F1 Case1 M 1 S 8 M0S7 M0S6 M0S5 M...

Страница 104: ...7 F18 F19 F8 F9 F10 F11 F0 F1 F2 F3 Data Out at linkclk T1 F28 F29 F30 F31 F20 F21 F22 F23 F12 F13 F14 F15 F4 F5 F6 F7 TX Error Reporting For TX path error reporting the transport layer expects a valid stream of TX data from the Avalon ST interface indicated by jesd204_tx_data_valid signal 1 as long as the jesd204_tx_data_ready remains asserted If the jesd204_tx_data_valid signal unexpectedly deas...

Страница 105: ... Latency 1 1 3 txframe_clk period Maximum 5 txframe_clk period for byte 3 Minimum 2 txframe_clk period for byte 0 1 4 1 txframe_clk period 2 1 3 txframe_clk period Maximum 4 txframe_clk period for byte 2 and byte 3 Minimum 3 txframe_clk period for byte 0 and byte 1 2 2 1 txframe_clk period 4 1 txframe_clk period 8 1 txframe_clk period RX Path The deassembler in the RX path consists of the tail bit...

Страница 106: ...lock rearranges the resulting data bits in a specific way according to the mapping scheme refer to Figure 5 2 Multiplexing block sends the multiplexed data to the Avalon ST interface determined by certain control signals from the RX control block Table 5 11 Deassembler Parameter Settings Parameter Description Value L Number of lanes per converter device 1 8 F Number of octets per frame 1 2 4 8 CS ...

Страница 107: ..._ BUS_WIDTH N CS while OUTPUT_BUS_WIDTH N M S OUTPU T_BUS_ WIDTH N CS Table 5 12 Deassembler Signals Signal Clock Domain Direction Description Control Unit rxlink_clk Input RX link clock signal This clock is equal to the RX data rate divided by 40 This clock is synchronous to the rxframe_clk signal rxframe_clk Input RX frame clock used by the deassembler The frequency is a function of parameters F...

Страница 108: ... interface is valid or invalid 0 data is invalid 1 data is valid jesd204_rx_data_ ready rxframe_clk Input Indicates that the Avalon ST sink interface is ready to accept data from the transport layer 0 Avalon ST sink interface is not ready to receive data 1 Avalon ST sink interface is ready to receive data Signal Clock Domain Direction Description Between Transport Layer and DLL jesd204_rx_link_ da...

Страница 109: ...ain 1 transport layer starts sampling jesd204_ rx_link_datain at the next clock cycle Connect this signal to the RX DLL jesd204_rx_ link_ready input pin jesd204_rx_link_ error rxlink_clk Output Indicates an empty data stream due to invalid data This signal is asserted high to indicate an error at the Avalon ST sink interface for example when jesd204_rx_data_valid 1 while jesd204_rx_data_ready 0 Th...

Страница 110: ...0 value always match the system parameter L value Runtime reconfiguration supports L fallback For static configuration set the maximum L and reconfigure csr_l to a smaller value during runtime This transport layer only supports higher index channels to be powered down To interleave the de commision channels you need to modify the interface connection from the DLL to transport layer Connect this si...

Страница 111: ...resolution This 5 bit bus represents the N value in zero based binary format For example if N 16 the csr_n 4 0 01111 This design example supports the following values 01011 01100 01101 01110 01111 Any programmed value beyond the supported range may result in undeterminable behavior in the transport layer You must ensure that the csr_n 4 0 value always match the system parameter N value Connect thi...

Страница 112: ... jesd204_rx_link_data_ready jesd204_rx_link_data_valid f2_div1_cnt jesd204_rx_link_datain 31 0 rxdata_mux_out 15 0 jesd204_rx_crtlout 0 jesd204_rx_data_valid jesd204_rx_data_ready junk xddcc bbaa junk junk junk xbbaa ddcc x4433 bbaa xddcc 4433 xddc xbba xbba xddc x443 xbba xddc x443 jesd204_rx_dataout 11 0 junk junk xddc xbba xbba xddc x443 xbba xddc x443 RX Data Reception This section explains wh...

Страница 113: ...n big endian format The RX path data remapping is the reverse of TX path data remapping Refer to Figure 5 7for the RX transport layer remapping operation The following tables show examples of data mapping for L 4 F 1 2 4 8 and M S 2 4 8 16 The configurations that the transport layer support are not limited to these examples Table 5 13 Data Mapping for F 1 L 4 F 1 Lane L3 L2 L1 L0 Data In F12 F13 F...

Страница 114: ... 1 M0S0 F2F6 M1S0 F10F14 4th frameclk cnt 3 jesd204_rx_ dataout 31 0 F11F15 F3F7 Case1 M 1 S 2 M0S0 F3F7 M0S1 F11F15 Case2 M 2 S 1 M0S0 F3F7 M1S0 F11F15 F1_ FRAMCL K_DIV 4 jesd204_rx_dataout 127 0 F11F15 F3F7 F10F114 F2F6 F9F13 F1F5 F8F12 F0F4 Table 5 14 Data Mapping for F 2 L 4 F 2 Lane L3 L2 L1 L0 Data In F12 F13 F14 F15 F8 F9 F10 F11 F4 F5 F6 F7 F0 F1 F2 F3 Supported M and S M S 4 for F 2 L 4 F...

Страница 115: ...V 2 jesd204_rx_dataout 127 0 F14F15 F10F11 F6F7 F2F3 F12F13 F8F9 F4F5 F0F1 Table 5 15 Data Mapping for F 4 L 4 F 4 Lane L3 L2 L1 L0 Data In F12 F13 F14 F15 F8 F9 F10 F11 F4 F5 F6 F7 F0 F1 F2 F3 Supported M and S M S 8 for F 4 L 4 F 4 supports either case1 M 1 S 8 case2 M 2 S 4 case3 M 4 S 2 or case4 M 8 S 1 F 4 jesd204_rx_ dataout 127 0 F14F15 F12F13 F10F11 F8F9 F6F7 F4F5 F2F3 F0F1 Case1 M 1 S 8 M...

Страница 116: ...S11 M0S10 M0S9 M0S8 M0S7 M0S6 M0S5 M0S4 M0S3 M0S2 M0S1 M0S0 RX Error Reporting For RX path error reporting the transport layer expects the AL to always be ready to sample the RX data as indicated by the jesd204_rx_data_ready signal equal to 1 as long as the jesd204_rx_data_valid remains asserted If the jesd204_rx_data_ready signal unexpectedly deasserts the transport layer reports the error to the...

Страница 117: ...al port and can be written to or read from the port The memory is organized into bytes that can be further divided into fields The SPI communicates using two data lines a control line and a synchronization clock A single SPI master can work with multiple slaves The SPI core logic is synchronous to the clock input provided by the Avalon MM interface When configured as a master the core divides the ...

Страница 118: ...th MOSI master output slave input and MISO master input slave output lines but with a single DATAIO pin you can use the ALTIOBUF Megafunction IP core configured with bidirectional buffer with the SPI master to convert the MOSI and MISO lines to a single DATAIO pin The DATAIO pin can be dynamically reconfigured as MOSI by asserting the output enable oe signal or as MISO by deasserting the oe signal...

Страница 119: ...ink and Frame Reset Clear tx_err rx_err0 and rx_err1 status registers Reconfiguration Done reconfig 1 b1 Memory Block ROM The control unit is a finite state machine FSM that works with multiple memory blocks ROMs Each ROM holds the configuration data required to configure the external converter or clock devices for each SPI slave A memory initialization file MIF contains the initial values for eac...

Страница 120: ...e is based on 24 bit SPI write only programming The last word must not be a valid data and must be set to all 1 s to indicate the end of the MIF or programming sequence This is because each converter device may have a different number of programmable registers and hence involves a different number of MIF words In this design example three ROMs are used by default for each external ADC DAC and cloc...

Страница 121: ...he transport layer uses the post divided frame_clk POLYNOMIAL_ LENGTH 7 9 15 23 31 7 Defines the polynomial length for the PRBS pattern generator and checker which is also the equivalent number of stages for the shift register If PRBS 7 is required set this parameter to 7 If PRBS 9 is required set this parameter to 9 If PRBS 15 is required set this parameter to 15 If PRBS 23 is required set this p...

Страница 122: ... default values of LMF 124 Table 5 19 Static and Dynamic Reconfiguration Parameter Values Supported Mode Link L M F Reference Clock Frame Clock Link Clock F1_ FRAMECLK_ DIV F2_ FRAMECLK_ DIV Static Bonded Non bonded 2 1 1 2 153 6 153 6 153 6 2 Bonded Non bonded 1 1 1 4 153 6 153 6 153 6 1 Bonded Non bonded 1 1 2 4 153 6 153 6 153 6 1 Bonded Non bonded 1 1 4 8 153 6 76 8 153 6 1 Bonded Non bonded 1...

Страница 123: ...igures show the datapath of single and multiple JESD204B links Figure 5 17 Datapath of A Single JESD204B Link Pattern Generator M 1 S 1 N 16 FRAMECLK_DIV 1 Pattern Checker Assembler LMF 211 S 1 N 16 Deassembler LMF 211 S 1 N 16 TX Base Core LMF 211 S 1 N 16 RX Base Core LMF 211 S 1 N 16 Duplex SERDES PHY 32 32 16 16 Avalon ST Avalon ST Avalon ST Avalon ST Transport Layer 0 JESD204B IP Duplex Core ...

Страница 124: ..._DIV 1 M 1 S 1 N 16 FRAMECLK_DIV 1 M 1 S 1 N 16 FRAMECLK_DIV 1 JESD204B IP Duplex Core 1 LMF 112 Run Time Reconfiguration The JESD204B IP core supports run time reconfiguration for the LMF and data rate settings The design example only demonstrates the following set of configuration To generate the design example with run time reconfiguration enabled the LMF and bonding mode parameters must match ...

Страница 125: ...mplementation sync_n LINK 1 0 link_clk Input Indicates a TX SYNC_N from the receiver This is an active low signal and is asserted 0 to indicate a synchronization request or error reporting mdev_sync_n LINK 1 0 link_clk Input Indicates a multidevice synchronization request at the TX path Synchronize signal combination should be done externally and then input to the JESD204B IP core through this sig...

Страница 126: ...or through this signal the JESD204B IP core uses the jesd204_rx_int signal to indicate an interrupt Signal Clock Domain Direction Description SPI miso sclk Input Output data from a slave to the input of the master mosi sclk Output Output data from the master to the inputs of the slaves sclk mgmt_clk Output Clock driven by the master to slaves to synchronize the data bits ss_n 2 0 sclk Output Activ...

Страница 127: ...wn the LMF configuration to 112 Set this signal to 1 to scale up the LMF configuration back to 222 runtime_datarate mgmt_clk Input Reconfigure the data rate at run time This value must be stable prior to assertion of reconfig signal 0 Downscale to data rate setting stored in PLL PHY and clock MIF 1 Upscale back to maximum data rate setting stored in PLL PHY and clock MIF Assuming the compile time ...

Страница 128: ...k1 Case 4 If F1 F2_FRAMECLK_DIV 1 LINK 2 denoted by link0 and link1 M 2 denoted by m0 and m1 S 1 N 16 avst_usr_din 15 0 link0 m0 15 0 avst_usr_din 31 16 link0 m1 15 0 avst_usr_din 47 32 link1 m0 15 0 avst_usr_din 63 48 link1 m1 15 0 avst_usr_din_valid frame_ clk Input Indicates whether the data from the Avalon ST source interface to the transport layer is valid or invalid 0 data is invalid 1 data ...

Страница 129: ...ase 4 If F1 F2_FRAMECLK_DIV 1 LINK 2 denoted by link0 and link1 M 2 denoted by m0 and m1 S 1 N 16 avst_usr_dout 15 0 link0 m0 15 0 avst_usr_dout 31 16 link0 m1 15 0 avst_usr_dout 47 32 link1 m0 15 0 avst_usr_dout 63 48 link1 m1 15 0 avst_usr_dout_valid frame_ clk Output Indicates whether the data from the transport layer to the Avalon ST sink interface is valid or invalid 0 data is invalid 1 data ...

Страница 130: ...in for the JESD204B IP core TX The interrupt signal is asserted when an error condition or synchronization request is detected jesd204_rx_int LINK 1 0 link_clk Output Interrupt pin for the JESD204B IP core RX The interrupt signal is asserted when an error condition or synchronization request is detected Example Feature Dynamic Reconfiguration The JESD204B IP core design example demonstrates dynami...

Страница 131: ...lock MIF ROM DAC MIF ROM ADC MIF ROM JESD MIF ROM Control Unit PLL MIF ROM PLL Reconfiguration Avalon MM Avalon MM Transceiver Reconfiguration Controller Avalon MM Avalon MM reconfig runtime_lmf runtime_datarate cu_busy Avalon MM 5 50 Dynamic Reconfiguration Operation UG 01142 2015 05 04 Altera Corporation JESD204B IP Core Design Guidelines Send Feedback ...

Страница 132: ...IF ROM contains the ADC converter setting DAC MIF ROM contains the DAC converter setting CLK MIF ROM contains the device clock setting MIF ROM You need to generate two MIF files for each reconfigurable IP core as shown in Figure 5 20 or Figure 5 21 and merge them into a single MIF file for each IP core The following section shows the MIF file format Core PLL The MIF format is fixed by the PLL You ...

Страница 133: ...0000000000000000111111 END OF MIF END PHY Stratix V and Arria V The MIF format is fixed by the PHY You need to generate two JESD204B IP cores with maximum and downscale setting Then compile each of the setting to get a total of four MIF files two for TX PLL and two for channel MIF Then merge the files into one phy mif Only the JESD204B IP cores with maximum configuration is used in final compilati...

Страница 134: ...with maximum and downscale setting Then compile each of the setting to get a total of four MIF files two for TX PLL and two for channel MIF Then merge the files into two xcvr_atx_pll_combined mif and xcvr_cdr_combined mif Only the JESD204B IP cores with maximum configuration is used in final compilation xcvr_atx_pll_combined mif Maximum Configuration MIF CONTENT BEGIN 00 102FF71 Start of MIF 01 10...

Страница 135: ...ESD The current JESD MIF contains only the LMF information You need to manually code the MIF content in the following format Maximum Configuration MIF WIDTH 16 DEPTH 16 ADDRESS_RADIX UNS DATA_RADIX BIN CONTENT BEGIN 0 0000000000000001 L maximum config 1 0000000000000001 M 2 0000000000000001 F 3 1111111111111111 End of MIF 4 7 0000000000000000 Downscale Configuration MIF 8 0000000000000000 L downsc...

Страница 136: ...11000000101 67 10000100000000000001110000000010 92 10000001000000001111111100000001 93 10000001000000000101111100010100 94 11111111111111111111111111111111 End of MIF 95 127 00000000000000000000000000000000 END Generating and Simulating the Design Example To use the JESD204B IP core design example testbench follow these steps 1 Generate the design example simulation testbench Refer to Generating t...

Страница 137: ...ator follow these steps 1 Start the ModelSim Altera simulator 2 On the File menu click Change Directory Select example_design_directory ed_sim testbench mentor 3 On the File menu click Load Macro file Select run_tb_top tcl This file compiles the design and runs the simulation automatically providing a pass fail indication on completion To simulate the design using the VCS MX simulator in Linux fol...

Страница 138: ...erate the Quartus II synthesis compilation files by running the script gen_quartus_synth tcl located in the example_design_directory ed_synth directory Note If you use the Quartus II Tcl console to generate the gen_quartus_synth tcl script close all Quartus II project before you start generating To compile your design using the Quartus II software follow these steps 1 Launch the Quartus II softwar...

Страница 139: ...the FPGA SYSREF signal sysref with respect to the FPGA device clock device_clk pin The trace length mismatch resulted in 500 ps or 0 5 ns difference in time arrival at the FPGA pins between SYSREF and device clock In most cases the register in the IP core which detects the SYSREF signal is far away from the SYSREF I O pin The long interconnect routing delay results in timing violation You are reco...

Страница 140: ...o 3 at least 5 times and record the RBD count values 5 Set the csr_rbd_offset accordingly with one LMFC count tolerance 6 Perform multiple power cycles and make sure lane de skew error does not occur using this RBD offset value The RBD count should be fairly consistent within 2 counts variation from one power cycle to another power cycle In the following examples the parameter values are L 1 F 1 a...

Страница 141: ...n safely release the elastic buffer 1 LMFC count earlier at LMFC count 7 before the next LMFC boundary If the RBD elastic buffer is released before the latest arrival lane this will cause a lane de skew error 1stLMFC boundary SYSREF pulse is sampled by IP core internal register 2 link clock cycle deterministic delay from SYSREF sampled high to1stLMFC boundary Link clock Free running LMFC counter I...

Страница 142: ... K RBD count 7 K K K K K K K K K K K Latest arrival lane in second power cycle R D D D RBD count 0 K K K K K D K K K K K Latest arrival lane in fifth power cycle D D D D R Next LMFC boundary RBD count 1 with reference to the current LMFC boundary K K K K K K K K K K K Aligned outputs on all lanes K R D D K K 1 link clock or LMFC count to cater for power cycle variation RBD Elastic Buffers Released...

Страница 143: ... to 1 2 or 3 is illegal because this exceeds the RBD elastic buffer size for the F and K configurations Related Information SYNC_N Signal on page 4 14 Programmable LMFC Offset If your JESD204B subsystem design has deterministic latency issue the programmable LMFC offset in the TX and RX IP cores provides flexibility to ensure that deterministic latency can be achieved The TX LMFC offset can align ...

Страница 144: ...s always released at the third LMFC boundary First LMFC boundary SYSREF pulse is sampled by IP core internal register 2 link clock cycle deterministic delay from SYSREF sampled high to the first LMFC boundary Free running LMFC counter Internal LMFC Counter 0 1 2 0 1 0 1 2 3 4 5 6 7 K SYNC_N deasserted directly after LMFC boundary K K K K R K K K K K Latest arrival lane in multiple power cycles D D...

Страница 145: ...h LMFC boundary 1 link clock period LMFC count Internal LMFC counter resets csr_lmfc_offset 0 7 Third LMFC boundary D D SYNC_N transmitted by RX R R Free running LMFC counter Internal LMFC Counter 3 4 5 6 7 0 1 3 4 5 6 7 0 1 2 3 RBD elastic buffer released when csr _rbd_offset 0 2 K K K K K K K K K K Internal LMFC counter resets csr_lmfc_offset 3 LMFC boundary is delayed by 5 link clock First LMFC...

Страница 146: ...unt 7 Third LMFC boundary Free running LMFC counter 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 7 SYSREF pulse is sampled by FPGA IP core SYNC_N transmitted by DAC 0 SYNC_N deassertion is detected by the IP core SYNC_N arrival at TX K K K K K R K K K K K L Transmit lanes D D D D K D D ILAS transmission by the FPGA Internal LMFC counter resets csr_lmfc_offset 0 First LMFC boundary Second LMFC boundary Third ...

Страница 147: ... 7 0 1 0 1 2 3 4 5 SYNC_N deasserted at the LMFC boundary 7 Third LMFC boundary Free running LMFC counter 0 1 2 3 7 0 1 2 3 SYSREF pulse is sampled by FPGA IP core SYNC_N transmitted by DAC 0 SYNC_N deassertion is detected by IP core SYNC_N arrival at TX K K K K R K K K K K L Transmit lanes D ILAS transmission by FPGA Internal LMFC counter resets csr_lmfc_offset 0 First LMFC boundary Second LMFC b...

Страница 148: ...et K 32 on the FPGA set the converter s K value to 32 as well Scrambling does not affect the link initiali zation in the CGS and ILAS phases but in the user data phase When scrambling is enabled on the ADC the FPGA descrambling option has to be turned on using the Enable scramble SCR option in the JESD204B IP core Qsys parameter editor When scrambling is enabled on the FPGA the DAC descram bling h...

Страница 149: ... Converter and FPGA Operating Conditions The transceiver channels at the converter and FPGA are bounded by minimum and maximum data rate requirements Always check the most updated device data sheet for this info For example the Arria V GT device has a minimum data rate of 611 Mbps Ensure that the sampling rate of the converter is within the minimum and maximum requirements For example the ADC AD92...

Страница 150: ...rify the RX PHY status through these signals in the ip_variant_name v rx_is_lockedtodata rx_analogreset rx_digitalreset rx_cal_busy Verify the TX PHY status through these signals in the ip_variant_name v pll_locked pll_powerdown tx_analogreset tx_digitalreset tx_cal_busy Verify the RX_TX PHY status through these signals in the ip_variant_name v rx_is_lockedtodata rx_analogreset rx_digitalreset rx_...

Страница 151: ...esd204_rx_int alldev_lane_aligned dev_lane_aligned rx_somf Use the rxlink_clk signal as the sampling clock Verify the TX PHY link layer interface operation through these signals in the ip_variant_name _inst_phy v jesd204_tx_pcs_data jesd204_rx_pcs_kchar_data Verify the TX link layer operation through these signals in the ip_variant_name v jesd204_tx_avs_rst_n txlink_rst_n_reset_n tx_sysref for Sub...

Страница 152: ...pon receiving 4 consecutive K characters the link layer deasserts the rx_dev_sync_n signal f The JESD204B link transition from CGS to ILAS phase when ADC transmit R or 1C hexadecimal after K character g Start of 2nd multi frame in ILAS phase 2nd multi frame contains the JESD204B link configuration data h Start of 3rd multi frame i Start of 4th multi frame j Device lanes alignment is achieved In th...

Страница 153: ...se with ramp pattern transmitted from the ADC Verify the TX transport layer operation using these signals in the altera_jesd204_transport_tx_top sv txframe_rst_n jesd204_tx_datain jesd204_tx_data_valid jesd204_tx_data_ready jesd204_tx_link_early_ready jesd204_tx_link_data_valid jesd204_tx_link_error Use the txframe_clk signal as the sampling clock For normal operation the jesd204_tx_data_valid jes...

Страница 154: ...04B IP core AN 729 Implementing JESD204B IP Core System Reference Design with Nios II Processor As Control Unit Altera Transceiver PHY IP Core User Guide More information about the transceiver PHY signals UG 01142 2015 05 04 Debugging JESD204B Link Using SignalTap II and System Console 7 7 JESD204B IP Core Debug Guidelines Altera Corporation Send Feedback ...

Страница 155: ...Riviera for Arria 10 devices only Updated Figure 8 16 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective...

Страница 156: ... page 3 11 Updated Figure 8 1 Figure 8 3 and Figure 8 4 Added a new table Register Access Type Convention to describe the access type for the IP core registers Added new signals description for jesd204_tx_controlout and jesd204_rx_controlout Added CONTROL_BUS_WIDTH parameter and description for the assembler and deassembler Added information on how to run the Tcl script using the Quartus II sofwar...

Страница 157: ...ation JESD204B IP Core Debug Guidelines Updated the Clocking scheme section Added new transceiver signals that is supported in Arria 10 devices Updated the Transport Layer section Added run time reconfiguration parameter values in the System Parameters section Updated the file directory names November 2013 2013 11 04 Initial release How to Contact Altera Table 8 1 Altera Contact Information Contac...

Страница 158: ...g Email authorization altera com Related Information www altera com support www altera com training www altera com literature 39 You can also contact your local Altera sales office or sales representative 8 4 How to Contact Altera UG 01142 2015 05 04 Altera Corporation Additional Information Send Feedback ...

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