Clock Signal
Formula
Description
TX/RX Link Clock:
txlink_clk
rxlink_clk
Data rate/40
The timing reference for the JESD204B IP core.The
link clock runs at data rate/40 because the IP core is
operating in a 32-bit data bus architecture after 8B/
10B encoding.
The JESD204B transport layer in the design
example requires both the link clock and frame
clock to be synchronous.
TX/RX Frame Clock
(in design example):
txframe_clk
rxframe_clk
Data rate/(10 × F)
The frame clock as per the JESD204B specification.
This clock is applicable to the JESD204B transport
layer and other upstream devices that run in frame
clock such as the PRBS generator/checker or any
data processing blocks that run at the same rate as
the frame clock.
The JESD204B transport layer in the design
example also supports running the frame clock in
half rate or quarter rate by using the
FRAMECLK_
DIV
parameter. The JESD204B transport layer
requires both the link clock and frame clock to be
synchronous. For more information, refer to the F1/
F2_FRAMECLK_DIV parameter description and
its relationship to the frame clock.
TX/RX Transceiver
Serial Clock and
Parallel Clock
Internally derived from
the data rate during IP
core generation
The serial clock is the bit clock to stream out
serialized data. The transceiver PLL supplies this
clock and is internal to the transceiver.
The parallel clock is for the transmitter PMA and
PCS within the PHY. This clock is internal to the
transceiver and is not exposed in the JESD204B IP
core.
For Arria V and Stratix V devices, these clocks are
internally generated as the transceiver PLL is
encapsulated within the JESD204B IP core's PHY.
For Arria 10 devices, you need to generate the
transceiver PLL based on the data rate and connect
the serial and parallel clock. These clocks are
referred to as
*serial_clk
and
*bonding_clock
in
Arria 10 devices. Refer to the
Arria10 Transceiver
PHY IP Core User Guide
for more information.
UG-01142
2015.05.04
Clocking Scheme
4-19
JESD204B IP Core Functional Description
Altera Corporation
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