Altera DE2 Board, Руководство по началу работы

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Lab 2: TV Box
51
Chapter
6
Chapter 6
Lab 2: TV Box
HDTV/SDTV is one of the most important multimedia technologies students and
engineers should learn to meet the huge industry demand in this area. In this lab,
we will implement a TV box using DE2 board.
6-1
Design Descriptions
Figure 6.1 illustrates the block diagram of the entire design. There are two major
blocks in the circuit – I2C_AV_Config and TV_TO_VGA blocks; the TV_TO_VGA
block consists of itu_r656_decoder, Dual Port Line Buffer, HsyncX2,
YCrCb2RGB, and VGA_Timing_Generator. The figure also shows the TV
decoder(ADV7181) and the VGA DAC(10-bit, ADV7123) chips used.
As soon as the bitstream is downloaded into the FPGA, the register values of the
TV Decoder chip requires will be used to configure the TV decoder via
I2C_AV_Config block, which is using I2C protocol to communicate with the TV
Decoder chip. After power-on sequence, the TV Decoder chip will have an
unstable period; Lock detector is responsible for detecting this unstable problem.
The itu_656_decoder block extracts YCrCb (4:4:4) Video signals from the 4:2:2
data source sent from the TV Decoder. It also generates a 13.5Mhz for pixel clock
(YPixel Clock) with the blanking signals indicating the valid period of data output.
Because the video signal from the TV Decoder is interlaced, we need to perform
the de-interlacing on the data source. We used the Dual Port Line Buffer block
and Hsyncx2 block to perform the de-interlacing operation where the pixel clock is
changed to 27Mhz from 13.5Mhz and the Hsync is changed to 31.4Khz from
15.7Khz. Inside the Dual Port Line Buffer uses a 1Kbyte long dual port SRAM to
double the YCrCb data amount (Yx2, Crx2, Cbx2 signals in the block diagram).
Finally, the YCrCb2RGB block converts the YCrCbx2 data into RGB output. The