ADM-XRC-II User Manual
4.
PCI Bus Interface
The PCI bus is implemented in a PLX PCI9656 and is configured with settings
as described later in this document to simplify the integration of user
applications in the FPGA.
The PCI configuration space of the ADM-XRC-II is shown below.
Config.
Offset
31
24
23 16
15 8
7
0
00 Device
ID
(0042)
(9656)
Vendor ID
(4144)
(10B5)
04 Status
Command
08 Class
Code
RevisionID
0C
BIST
HeaderType Lat. Timer Cache Line
10 PCI
BAR0
(PLX Internal Registers/Memory)
14 PCI
BAR1
(PLX Internal Registers/IO)
18 PCI
BAR2
(Local Bus FPGA)
1C PCI
BAR3
(Local Bus Control/Flash/SelectMap)
20 PCI
BAR4
(Not used)
24 PCI
BAR5
(Not used)
28
Card Bus CIS Pointer(Not used)
2C
Subsystem ID
Subsystem Vendor ID
30
PCI Base Address for Local Expansion ROM
34 Reserved
38 Reserved
3C
Max Lat
Min Gnt
Int. Pin
Int. Line
The PCI9656 uses the first two Bar’s to provide access to its internal registers
both via memory accesses and I/O accesses. Either BAR may be used by the
host.
BAR 2 provides access to a 4Mbyte space for use by the FPGA and must be
accessed only when a valid FPGA configuration is loaded that can respond
correctly to local bus access.
BAR 3 provides access to the local control registers and the flash memory.
ADM-XRC-II User Manual
Version 1.5
Page 4