ADM-XRC-II User Manual
5.7. Synchronous
SRAM
The four banks of synchronous SRAM are identical in device type and FPGA
interface. The devices fitted as pipelined ZBT parts organised as 256Kx32/36
bits each.
The pins are allocated to support synchronous burst or ZBT SRAM and each
bank provides the following interface.
FPGA Pin Active
Type
Function
RD
n
[36:0]
high Bidir
Data
Bus
RA
n
[19:0]
high OUT
Address
Bus
RC
n
[3:0]
low
OUT
Byte enables
RC
n
[4]
low
OUT
Global write enable
RC
n
[5]
low OUT
Chip
enable
RC
n
[6]
low
OUT
ADV (advance) function
RC
n
[7]
low OUT
Output
enable
RCn[8]
low
OUT
CKE - clock enable
Where
n
= 0,1,2,3,4,5. Therefore, SRAM 0 is controlled by the three bus ports
RD0[36:0], RA0[19:0] and RC0[8:0] and these are names used to constrain
the pins in the user constraints file or UCF.
5.8. Clock
pins
The six banks of SRAM are divided into two clock domains. Each SRAM clock
domain has its own pin routed from the FPGA.
ramclk[0]
OUT
Clock to SRAM 0, SRAM 1, SRAM 2
ramclk[1]
OUT
Clock to SRAM 3, SRAM 4, SRAM 5
ramclk_fb[0]
INPUT
Clock feedback for ramclk[0]
ramclk_fb[1]
INPUT
Clock feedback for ramclk[1]
Clock Domain 0
Clock Domain 1
Sram 0 Clk
Sram 1 Clk
Sram 2 Clk
Sram 3 Clk
Sram 4 Clk
Sram 5 Clk
IBufg
IBufg
OBuf
OBuf
ramclk[0]
ramclk[1]
ramclk_fb[0]
ramclk_fb[1]
to/from
Virtex DCM
to/from
Virtex DCM
Virtex II Device
ADM-XRC-II User Manual
Version 1.5
Page 13
