ADM-XRC-II User Manual
5.6. Local
Bus
The local bus of the ADM-XRC-II uses the PCI9656 to provide a non-
multiplexed address and data capability with synchronous speeds of up to
66MHz, independent of PCI operation. Whilst the local bus is capable of
achieving near PCI performance, it is much simpler to interface with than PCI.
The ADM-XRC-II routes most of the local bus signals to the FPGA and
devotes an entire address space to the FPGA.
The signals provided are :-
Signal Active Direction Purpose
LA[31:2] high
IN Address
LBE[3:0} low
IN Address/byte
enables
LD[31:0] high BIDIR Data
Bus
LWRITE
high
IN
Write cycle when true, read when false
LBLASTL
low
IN
End of burst
LADSL
low
IN
Address / data start
LBTERML low OUT/TRI
Burst
terminate
LREADYIL
low
OUT/TRI Accepts/completes data transfer
LDREQL[1:0]
low
OUT
Request DMA transfer
LDACKL[1:0]
low
IN
DMA transfer acknowledge
LEOTL[1:0]
low
OUT
Terminate current DMA transfer
LINTIL
low
OUT
Interrupt (via CPLD)
FHOLD
high
OUT
Reserved for future use
FHOLDA
high
IN
Reserved for future use
LRESETOL
low
IN
Reset from PLX and PCI
LCLKA
high
IN
Local bus clock (VCLK from ICS9161)
The local bus provides 8Mbytes of address space for the FPGA to use for
whatever purpose is desired by the application. LA[23]=0 should be used to
determine when the FPGA is being accessed.
Example Verilog code demonstrates how to interface to the local bus and
provide access to the SSRAM’s for test purposes. User applications can
define how the address space allocated to the FPGA is mapped to the local
bus and may or may not provide access to the SRAM memory.
ADM-XRC-II User Manual
Version 1.5
Page 12
