ADM-XRC-II User Manual
3. Board
Overview
The ADM-XRC-II PMC provides an easy way to achieve PCI performance
without the need to develop or incorporate PCI cores into the FPGA design.
The benefit provided by this architecture means faster development time and
reduced cost in evaluating and testing FPGA applications.
The XRC effectively connects the FPGA directly to the local bus of the
PCI9656 to enable two main modes of operation, slave and master. A
Complex Programmable Logic Device or CPLD also resides on the local bus
and manages access to resources such as flash, SelectMAP and the clock
generator.
In direct slave mode, the XRC is a target on the PCI bus for read and write
transactions and these are translated into local bus cycles initiated by the
PCI9656.
In direct master mode, the FPGA can request control over the local bus and
initiate transactions to the PLX. These transactions are translated by the PLX
into PCI master operations to read or write another PCI target.
In both master and slave modes of operation the FPGA can use burst
capability to boost performance and achieve very high data transfer rates. In
most PC systems, 240MB/s is achievable but this can vary depending on the
quality of the PC chipset and the ability of the BIOS to configure PCI devices
correctly.
ADM-XRC-II User Manual
Version 1.5
Page 3
