ADM-XRC-9R1 User Manual
V1.7 - 16th Sept 2020
3.4.7.1 Sysref Clocks
The sysref clocks provide the sysref functionality to synchronize the RF DACs and ADCs. They are provided by
the RF clock generators. They are connected to the PL and the RF sampling block.
Signal
Frequency
Target FPGA Input
"P" pin
"N" pin
FPGA Sysref Clock
Variable
IO_L6_HDGC_88
G12
F12
RF Sysref Clock
Variable
SYSREF_228
N5
N4
Table 11 : SysRef Connections
3.4.7.2 RF System FPGA Reference Clock
The RF system FPGA reference clock is a differential clock signal from the RF clock generation circuit, and is
connected to an HDGC input on the PL.
Signal
Frequency
Target FPGA Input
"P" pin
"N" pin
RF System FPGA
Reference Clock
Variable
IO_L5P_HDGC_88
F14
F13
Table 12 : FPGA Reference Clock Connections
Page 13
Functional Description
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