Alpha Data ADM-XRC-7V1, Руководство пользователя

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ADM-XRC-7V1 User Manual
V1.9 - 23rd Aug 2016
Appendix A Rear Connector Pinouts ............................................................................................................... 23
A.1
Primary XMC Connector, P5 ........................................................................................................ 23
A.2 Secondary XMC Connector, P6 ................................................................................................... 24
A.2.1 Pn6 GPIO Pin Map .................................................................................................................. 25
A.3 PMC Connector P4 ...................................................................................................................... 27
A.4 Rear MGT Connections to the Target FPGA ............................................................................... 28
Appendix B Front (XRM) Connector Pinouts ................................................................................................... 30
B.1
XRM Connector CN1, Field 1 ...................................................................................................... 31
B.2 XRM Connector CN1, Field 2 ...................................................................................................... 32
B.3 XRM Connector CN1, Field 3 ...................................................................................................... 33
B.4 XRM Connector CN2 ................................................................................................................... 34
List of Tables
Table 1 References ........................................................................................................................................ 1
Table 2 Switch Definitions .............................................................................................................................. 5
Table 3 LED Definitions .................................................................................................................................. 6
Table 4 REFCLK200M Connections ............................................................................................................. 10
Table 5 PCIEREFCLK Connections ............................................................................................................. 10
Table 6 PROGCLK Connections .................................................................................................................. 11
Table 7 GCLK_M2C Connections ................................................................................................................. 11
Table 8 MGTCLK_M2C Connections ........................................................................................................... 11
Table 9 XRM_LVDS_CLK Connections ........................................................................................................ 12
Table 10 Voltage and Temperature Monitors .................................................................................................. 15
Table 11 Temperature Limits .......................................................................................................................... 16
Table 12 Status LED Definitions ..................................................................................................................... 16
Table 13 Target FPGA IO Banks .................................................................................................................... 17
Table 14 Target MGT Links ............................................................................................................................ 17
Table 15 Maximum Memory Speeds .............................................................................................................. 19
Table 16 XRM GPIO Groups .......................................................................................................................... 20
Table 17 Pn5 Interface ................................................................................................................................... 23
Table 18 Pn6 Interface ................................................................................................................................... 24
Table 19 Pn6 GPIO Pin Map .......................................................................................................................... 25
Table 20 Pn4 Interface ................................................................................................................................... 27
Table 21 Target RearMGT Mapping ............................................................................................................... 28
Table 22 XRM Connector CN1, Field 1 .......................................................................................................... 31
Table 23 XRM Connector CN1, Field 2 .......................................................................................................... 32
Table 24 XRM Connector CN1, Field 3 .......................................................................................................... 33
Table 25 XRM Connector CN2 ....................................................................................................................... 34
List of Figures
Figure 1 ADM-XRC-7V1 Block Diagram .......................................................................................................... 4
Figure 2 LED Locations ................................................................................................................................... 6
Figure 3 JTAG Header J1 ................................................................................................................................ 8
Figure 4 JTAG Boundary Scan Chain .............................................................................................................. 8
Figure 5 Clocks ................................................................................................................................................ 9
Figure 6 Flash Memory Map .......................................................................................................................... 13
Figure 7 MGT Links ....................................................................................................................................... 18
Figure 8 DRAM Banks ................................................................................................................................... 19