ADM-XRC-7V1 User Manual
V1.9 - 23rd Aug 2016
3.5 Flash Memory
A 512Mb Flash Memory (Intel / Numonyx PC28F512P30EF) is used to store board Vital Product Data (VPD),
programmable clock parameters and configuration bitstreams for the Bridge and Target FPGAs.
The flash memory cannot be accessed by the target FPGA. Host access is only possible through the FLCTL,
FLPAGE and FLDATA registers in the Bridge FPGA.
The region of memory between addresses 0x11000000 and 0x11FFFFF is allocated for custom data to be stored
by the ADM-XRC-7V1 user.
Utilities for erasing, programming and verification of the flash memory are provided in the ADMXRC SDK.
Write Protect
The Flash Write Protect (WP#) pin is connected to an inverted version of the NVMRO signal at the XMC
interface. When the NVMRO signal is active (High), all writes to the flash will be inhibited. This state will be
indicated by the Amber LED as shown in
0x0000_0000
0x007F_FFFF
Alternate Bridge FPGA Bitstream
Default Bridge FPGA Bitstream
0x0080_0000
0x00FF_FFFF
0x0100_0000
0x010F_FFFF
B0 Length(7:0)
Boot Flag 0
Bitstream 0 Length(23:8)
reserved
Default Target FPGA Bitstream
(Target Bitstream 0)
0x0122_0000
0x028F_FFFF
0x0120_0000
0x0120_0002
B1 Length(7:0)
Boot Flag 1
Bitstream 1 Length(23:8)
reserved
Alternate Target FPGA Bitstream
(Target Bitstream 1)
0x0292_0000
0x03FF_FFFF
0x0290_0000
0x0290_0002
0x0110_0000
0x011F_FFFF
Alpha Data Vital Product Data
(Alpha Data VPD)
User Vital Product Data
(User VPD)
Figure 6 : Flash Memory Map
Page 13
Functional Description
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