Alpha Data ADM-XRC-7V1, Руководство пользователя

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ADM-XRC-7V1 User Manual
V1.9 - 23rd Aug 2016
3.8 Local Bus
A Multiplexed Packet Transport Link (MPTL) connects the Bridge and Target FPGAs. It is capable of transferring
data at up to 2GB/s simultaneously in each direction.
The MPTL replaces the parallel local bus used in previous generations of the ADM-XRC series. Details of the
link and example designs are given in the Software Development Kit (SDK).
3.9 Target FPGA
3.9.1 I/O Bank Voltages
The Target FPGA IO is arranged in banks, each with their own supply pins. The bank numbers, their voltage and
function are shown in Target FPGA IO Banks . Full details of the IOSTANDARD required for each signal are
given in the SDK.
IO Banks Voltage Purpose
0, 14 1.8V
Configuration, JTAG, LBus Control,XMC
Control,Target SelectMap Interface
13, 33 1.8V Pn4 & Pn6 GPIO
15, 16, 17 XRM_VIO XRM Interface (variable voltage)
18, 19, 34, 35, 36,
37, 38, 39
1.5V DRAM Banks 0-3
Table 13 : Target FPGA IO Banks
3.9.2 Target MGT Links
There are a total of 26 Multi-Gigabit Transceiver (MGT) links connected to the Target FPGA:
Links Width Connection
PCIe(3:0) 4
Bridge FPGA (for MPTL) or XMC Connector
P5 lanes (3:0) in Bridge Bypass Mode
PCIe(7:4) 4 Direct link to XMC P5 lanes (7:4)
P6(9:0) 10 Direct link to XMC P6 lanes (9:0)
FrontMGT(7:0) 8 Direct link to XRM interface
Table 14 : Target MGT Links
The connections of these links are shown in MGT Links :
For MGT Clocking see Clocks :
Page 17 Functional Description
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