ADM-XRC-5T2-ADV User Manual
ADM-XRC-5T2-ADV User Manual
The clock buffer has a PLL with a minimum input frequency of 24MHz, potentially causing
problems in applications that use the PCI 33MHz mode with a slow clock. In this case, the
buffer can be bypassed to provide full PCI 33MHz compatibility.
4.6.
User FPGA
4.6.1. Configuration
The ADM-XRC-5T2-ADV performs configuration from the host at high speed using
SelectMAP. The FPGA may also be configured from flash or by JTAG via header J2.
Download from the host is the fastest way to configure the User FPGA with 8 bit SelectMAP
mode enabled. This permits an ideal configuration speed of up to 40MB/s.
The ADM-XRC-5T2-ADV can be configured to boot the User FPGA from flash on power-up if
a valid bit-stream is detected in the flash. Booting from flash will also configure the
programmable clocks.
Version 1.0
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