ADM-XRC-5T2-ADV User Manual
ADM-XRC-5T2-ADV User Manual
Signal FPGA
Pin
GTP
Number
P15 Pin
PCIE_TX0_P AB2 114A A1
PCIE_TX0_N AC2 “ B1
PCIE_RX0_P AC1 “ A11
PCIE_RX0_N AD1 “ B11
PCIE_TX1_P AG2 114B D1
PCIE_TX1_N AF2 “ E1
PCIE_RX1_P AF1 “ D11
PCIE_RX1_N AE1 “ E11
PCIE_TX2_P AH2 118A A3
PCIE_TX2_N AJ2 “ B3
PCIE_RX2_P AJ1 “ A13
PCIE_RX2_N AK1 “ B13
PCIE_TX3_P AN2 118B D3
PCIE_TX3_N AM2 “ E3
PCIE_RX3_P AM1 “ D13
PCIE_RX3_N AL1 “ E13
PCIE_TX4_P AP2 122A A5
PCIE_TX4_N AR2 “ B5
PCIE_RX4_P AR1 “ A15
PCIE_RX4_N AT1 “ B15
PCIE_TX5_P AW2 122B D5
PCIE_TX5_N AV2 “ E5
PCIE_RX5_P AV1 “ D15
PCIE_RX5_N AU1 “ E15
PCIE_TX6_P BA1 126A A7
PCIE_TX6_N BA2 “ B7
PCIE_RX6_P BB2 “ A17
PCIE_RX6_N BB3 “ B17
PCIE_TX7_P BA6 126B D7
PCIE_TX7_N BA5 “ E7
PCIE_RX7_P BB5 “ D17
PCIE_RX7_N BB4 “ E17
Table 11 XMC P15 Connections
4.10.
ADV212 Interface
The ADV212 is a single-chip JPEG 2000 codec from Analog Devices. It is targeted for video and
high bandwidth image compression applications that can benefit from the enhanced quality and
features provided by the JPEG 2000 (J2K)—ISO/IEC15444-1 image compression standard. The
ADM-XRC-5T2-ADV features 4 ADV212 devices which can all operate independently or in 2 banks
of 2 for full frame capabilities.
4.10.1. Signal Description
See the ADV212 data sheet and associated literature for a full description of the operation of
these pins.
Signals common to each ADV212 bank
addr<1> to <3>
-ADV212 address bus
mclk
-ADV212 system clock
vclk
-ADV212 video data bus clock
hdat<0> to <31>
-ADV212 host data bus
field
-ADV212 field sync for video mode
hsync
-ADV212 horizontal sync for video mode
vsync
-ADV212 vertical sync for video mode
jpeg_reset_l
-asynchronous processor reset for ADV212’s
scomm5
-synchronisation signal for multi-chip operation
Version 1.0
Page 14
