ADM-XRC-5T2-ADV User Manual
ADM-XRC-5T2-ADV User Manual
4.5.2. REFCLK
In order to make use of the IODELAY features of Virtex™-5, a stable low-jitter clock source is
required to provide the base timing for tap delay lines in each IOB in the User FPGA. The
ADM-XRC-5T2-ADV is fitted with a 200MHz LVPECL (LVDS optional) oscillator connected to
global clock resource pins. This reference clock can also be used for application logic if
required.
4.5.3. PCIe Reference Clock
A 100MHz PCIe reference clock input from the Primary XMC connector (Pn15) is connected
to one of the dedicated MGT clock inputs on the user FPGA. (See Table 3 for details of the
MGT clock connections.)
4.5.4. User MGT Clocks
A programmable, low-jitter clock source is provided by an ICS843034-01 “FemtoClocks”
frequency synthesiser. The synthesiser has two source crystals – one at 26.5625MHz (for
Fibre Channel applications) and another at 25.0MHz (suitable for PCIe, Gigabit Ethernet
etc.). The synthesiser also has two clock outputs.
”USERMGT_CLKA” is connected to an MGT clock input on the top-half of the user FPGA. It
may be used as an alternative to the PCIe reference for the MGTs connected to the Primary
XMC.
”USERMGT_CLKB” is connected to an MGT clock input on the bottom half of the user FPGA.
It may be used as the reference for the front user MGTs. (See Table 3 for details of the MGT
clock connections.)
Note: Either of these clocks can provide a programmable source for applications that do not
use MGTs.
4.5.5. FCN MGT Clock
A 156.25MHz precision oscillator is fitted on the ADM-XRC-5T2-ADV for Gigabit Serial I/O
applications. There are also 3 other options for clock inputs to the MGT tiles of the FPGA.
The oscillator frequency can be customised to suit applications requiring specific baud rates.
Contact the factory for details.
Clock Name
GTP
No.
FPGA Pin (P/N)
Reference for:
PCIE_REFCLK
114
AD4 / AD3
Primary XMC (Pn15) MGTs
USERMGT_CLKA
118
AK4 / AK3
Primary XMC (Pn15) MGTs
FCN_MGTREF
124
C4 / C3
Front (CN2) user MGTs
USERMGT_CLKB
112
V4 / V3
Front (CN2) user MGTs
Table 3 MGT Clock Connections
4.5.6. Rear (Pn4) Clocks
Four pairs of signals from Pn4 are connected to clock-capable inputs that can be used for
regional clocking of the remaining Pn4 signals. See Table 9 for details.
4.5.7. PCI Clocks
The PCI Interface within the bridge FPGA requires a regional clock input for 66MHz PCI
operation or a global clock input for PCI-X. To comply with the single-load requirement in the
PCI specification, a zero-delay clock buffer is used to route the PCI clock to the two different
clock inputs.
Version 1.0
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