ADM-SDEV-BASE/XCKU060 User Manual
V1.0 - 27th November 2018
3.4 Configuration
There are two main ways of configuring the FPGA on the ADM-SDEV-BASE:
•
From Flash memory on the config FMC board, at power-on, as described in
Section 3.4.1
•
Using a Xilinx Platform JTAG cable connected to the programming header on the config FMC board
Section 3.4.2
3.4.1 Configuration From ADM-SDEV-CFG1 Flash Memory
The FPGA can be automatically configured at power-on from two 256 Mbit QSPI flash memory device configured
as an x8 SPI device (Micron part numbers MT25QU256ABA8E12-1SIT). These flash devices are typically
divided into two regions of 32 MiByte each, where each region is sufficiently large to hold an uncompressed
bitstream for the FPGA.
It is possible to use Multiboot with a fallback image on this hardware. The master SPI configuration interface and
the Fallback MultiBoot are discussed in detail in Xilinx UG570.
The flash address map is as detailed below:
D
at
a
R
eg
io
n
Region 0
Default
(32 MiB)
Region 1
Multi-boot
(32 MiB)
Start Address (Bytes)
0x000_0000
0x200_0000
Figure 6 : Flash Address Map
At power-on, the FPGA attempts to configure itself automatically in serial master mode based on the contents of
the header in the programing file. See Xilinx UG570 MultiBoot for details.
Note:
If an over-temperature alert is detected from the System Monitor, the FPGA will be cleared by pulsing its
PROG signal. See
Automatic Temperature Monitoring
.
3.4.1.1 Building and Programming Configuration Images
Generate a bitfile with these constraints (see xapp1233):
•
set_property BITSTREAM.GENERAL.COMPRESS TRUE [ current_design ]
•
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
•
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
•
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design]
•
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
•
set_property BITSTREAM.CONFIG.UNUSEDPIN {Pullnone} [current_design]
•
set_property CFGBVS GND [ current_design ]
•
set_property CONFIG_VOLTAGE 1.8 [ current_design ]
•
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
Generate an MCS file with these properties (write_cfgmem):
•
-format MCS
•
-size 64
•
-interface SPIx8
Page 11
Functional Description
ad-ug-1360_v1_0.pdf
