PX848PV Series
25
HDD S.M.A.R.T. Capability
Self Monitoring Analysis and Reporting Technology is a technology that enables a PC to attempt to
predict the possible failure of storage drives. Options: Disabled (default)
、
Enabled
Intel OSB Logo Show
This item allows you to show or hide the Intel OSB logo. Options: Enabled (default)
、
Disabled
Advanced Chipset Features
DRAM Timing Selectable
This item determines DRAM clock/ timing using SPD or manual configuration.
Make sure your memory module has SPD (Serial Presence Data), if you want to select the “By SPD”
option. Options: Manual
、
By SPD (default)
CAS Latency Time
This item determines CAS Latency. When synchronous DRAM is installed, the number of clock
cycles of CAS latency depends on the DRAM timing. Do not reset this field from the default value
specified by the system designer. This field is adjustable only when “DRAM Timing Selectable” is
set to “Manual”. Options: 2
、
2.5
、
3 and By SPD (default)
Active to Precharge Delay
This item allows you to select DRAM Active to Precharge Delay.
Options: 8
、
7
、
6
、
5 and default is by SPD
DRAM RAS# to CAS# Delay
This item allows you to select a delay time between the CAS and RAS strobe signals. It only applies
when DRAM is written to, read from, or refreshed. This field is adjustable only when “DRAM
Timing Selectable” is set to “manual”. Options: 4
、
3
、
2 and default is by SPD
DRAM RAS# Precharge
This item allows you to select the DRAM RAS# precharge time. The ROW address strobe must
precharge again before DRAM is refreshed. An inadequate configuration may result in incomplete
data. This field is adjustable only when “DRAM Timing Selectable” is set to “manual”.
Options: 4
、
3
、
2 and By SPD (default)
System BIOS Cacheable
When enabled, accesses to system BIOS ROM addressed at F0000H-FFFFFH are cached, provided
that the cache controller is enabled. Options: Enabled (default), Disabled
