Aiwa FM-LMD811, Руководство по обслуживанию

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BCKI
XUGF
XPCK
GFS
C2PO
XTSL
C4M
DOUT
EMPH
EMPHI
WFCK
SCOR
SBSO
EXCK
SYSM
AVS11
AVD1
AOUT1
AIN1
LOUT1
AVS12
XVDD
XTAI
XTAO
XVSS
AVSS2
ROUT2
AIN2
AOUT2
AVD2
AVS21
XRST
Pin No. Pin Name I/O Description
44
47
48
49
50
51
52
53
54
55
56
57
58
59
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
I
O
O
O
O
I
O
O
O
I
O
O
O
I
I
—
—
O
I
O
—
—
I
O
—
—
O
I
O
—
—
I
D/A interface bit clock input.
XUGF output, MNT1 or RPCK output by switching command. (Not used)
XPLCK output, MNT0 output by switching command. (Not used)
GFS output, MNT3 or XRAOF output by switching command. (Not used)
C2PO output, GTOP output by switching command. (Not used)
X’tal select input terminal, X’tal: 16.9344MHz = “L” 33.8688MHz = “H”.
(Connected to GND)
4.2336MHz output, Output 1/4 divided frequency of VCKI at CAV-W mode.
(Not used)
Digital Out connector output signal.
“H” when the playback disc has emphasis. “L” when it does not.
De-emphasis ON/OFF, “H” when ON, “L” when OFF.
WFCK output. (Not used)
H output when the subcode sync S0 or S1 is detected. (Not used)
Serial output for SubP-W. (Not used)
SBSO read out clock input. (Connected to GND)
Mute input terminal, Active the “H” setting. (Connected to GND)
Analogue GND.
Analogue power supply. (+5V)
Lch/analogue output terminal.
Lch/OP AMP input terminal.
Lch/LINE output terminal.
Analogue GND.
Power supply for master clock.
Input terminal for crystal oscillator circuit.
Input external master clock from this terminal.
Output terminal for crystal oscillator circuit.
GND terminal for master clock.
Analogue GND.
Rch/LINE output terminal.
Rch/OP AMP input terminal.
Rch/analogue output terminal.
Analogue power supply. (+5V)
Analogue GND.
Reset system at “L” setting.
Note:
• PCMD is the two’s complement output with MSB first.
• GTOP monitors the protection status of the Frame Sync. (H: Sync protection window opened).
• XUGF is the Frame Sync negative pulse which is obtained from the EFM signal. This is the signal before the sync protection.
• XPLCK is the inverted signal of the EFM PLL clock. The PLL works so that the fall-down edge and the changed point of the
EFM signal agree.
• GFS is the signal that goes “H” when the Frame Sync and the internally inserted timing agree.
• RFCK is the signal having 136 micro-seconds (during normal speed) that is generated to have the same accuracy as X’tal.
• C2PO is the signal indicating the error status of the data.
• XRAOF is the signal that is generated when the 16k RAM goes outside the jitter margin
±
4F.