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The full set of error and status registers and the individual bits they contain is shown in the
Status Model Diagram and described in detail below, but in brief the status is maintained using
five primary registers, the Limit Event Status Register for each output, the Standard Event
Status Register and the Execution Error Register. A summary is reported in the Status Byte
Register, as selected by four masking registers, the Limit Status Enable Register for each
output and the Standard Event Status Enable Register. Two further mask registers, the Service
Request Enable register and the Parallel Poll Response Enable register, control operation of
the GPIB hardware Service Request and Parallel Poll (and the associated
ist
message)
respectively. It is recommended that, when controlling the unit through any interface other than
GPIB, the controller program should simply read the primary status registers directly.
The Standard Event Status Register, supported by the Execution Error and Query Error
registers, records events concerned with command parsing and execution, and the flow of
commands, queries and responses across the interface. These are mainly of use during
software development, as a production test procedure should never generate any of these
errors.
Limit Event Status and Limit Event Status Enable Registers
This pair of registers are implemented for each output as an addition to the IEEE Std.488.2.
Their purpose is to inform the controller of entry to and/or exit from current or voltage limit
conditions and the history of protection trip conditions since the last read.
Any bits set in the Limit Event Status Register (LSR<
N
>) which correspond to bits set in the
Limit Event Status Enable Register (LSE<
N
>) will cause the LIM<
N
> bit to be set in the Status
Byte Register, where <
N
> is 1 for output 1, 2 for output 2, 3 for output 3 and 4 for output 4.
The Limit Event Status Register is read and cleared by the LSR<
N
>? command. The Limit
Event Status Enable Register is set by the LSE<
N
> <
NRF
> command and read by the LSE<
N
>?
command.
Bit 7 - Reserved for future use
Bit 6 - Set when a fault trip has occurred which requires AC power OFF/ON to reset.
Bit 5 - Reserved for future use
Bit 4 - Set when an output over temperature trip has occurred
Bit 3 - Set when an output over current trip has occurred
Bit 2 - Set when an output over voltage trip has occurred
Bit 1 - Set when output enters current limit (constant current mode)
Bit 0 - Set when output enters voltage limit (constant voltage mode)
Standard Event Status Registers (ESR and ESE)
The Standard Event Status Register is defined by the IEEE Std. 488.2 GPIB standard. It is a bit
field, where each bit is independent and has the following significance:
Bit 7
Power On.
Set when power is first applied to the instrument.
Bits 6 & 1:
Not used, permanently 0.
Bit 5
Command Error.
Set when a syntax error is detected in a command or parameter.
The parser is reset and parsing continues at the next byte in the input stream.
