Agilent Technologies ESA-E E4401B, Справочник пользователя/программиста

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Chapter 4 229
Status Registers
Use Status Registers to Determine the State of Analyzer Events and Conditions
Stat
us Re
giste
rs
Bit Decimal
Value
Description
0 1
Reserved
: This bit is not used by the analyzer, but is for
future use with other Agilent products.
1
a
2
No Result Available
: A 1 in this bit position
indicates that a measurement terminated with no
measurement results.
2
a 4 Measurement Timeout : A 1 in this bit position
indicates that a measurement terminated due to a timeout.
3 8 Data Uncalibrated Summary : This is the summary
bit for the Questionable Status Integrity Uncalibrated
Register.
4 16
IF/ADC Over Range
: The signal input level is too high,
causing the analyzer analog-to-digital converter (ADC)
range to be exceeded. This may occur with resolution
bandwidths less than or equal to 300 Hz in zero span.
5
a 32 Over Range : A 1 in this bit position indicates that the
signal is too large at the analog-to-digital converter (ADC).
6
a 64 Under Range : A 1 in this bit position indicates that the
signal is too small at the analog-to-digital converter (ADC).
7
a
128
Insufficient Data
: A 1 in this bit position indicates
that there is not enough information to perform the
measurement or function.
8
a 256 Acquisition Failure : A 1 in this bit position
indicates that the demod algorithm cannot correlate to the
signal.
9
a 512 Memory Problem : A 1 in this bit position indicates a
failure of the file system memory or digital signal processor
(DSP) memory.
10
a
1024
Auto-Trigger Timeout
: A 1 in this bit position
indicates that the measurement timed out due to no trigger.
11
a 2048 Trigger Problem : A 1 in this bit position indicates that
the measurement timed out due to no trigger.
12 4096 Invalid Data : A 1 in this bit position indicates that the
present trace data does not reflect the existing analyzer
state. Trigger a new sweep and/or measurement.
13
a
8192
Unidentified Error
: A 1 in this bit position indicates
that a measurement has terminated for a reason other than
that given in any of the other bits.