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206 Chapter 4
Status Registers
Use Status Registers to Determine the State of Analyzer Events and Conditions
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The status byte register contains the following bits:
To query the status byte register, send the *STB command. The response will be the decimal sum of the
bits that are set to 1. For example, if bit number 7 and bit number 3 are set to 1, the decimal sum of the 2
bits is 128 plus 8. So the decimal value 136 is returned.
Service Request Enable Register
In addition to the status byte register, the status byte group also contains the service request enable
register. The status byte service request enable register lets you choose which bits in the Status Byte
Register will trigger a service request.
Send the
*SRE <number>
command (where
<number>
is the sum of the decimal values of the bits you
want to enable plus the decimal value of bit 6). For example, assume that you want to enable bit 7 so that
whenever the operation status summary bit is set to 1, it will trigger a service request. Send the
*SRE
192
(128 + 64) command. The
*SRE?
command returns the decimal value of the sum of the bits enabled
previously with the *SRE <number> command.
Bit Decimal
Value
Description
0 1
Unused
: This bit is always set to 0.
1 2
Unused
: This bit is always set to 0.
2 4 Error/Event Queue Summery Bit : A 1 in this bit position
indicates that the SCPI error queue is not empty. The SCPI error
queue contains at least one error message.
3 8
Questionable Status Summary Bit
: A 1 in this bit
position indicates that the questionable status summary bit has
been set. The questionable status event register can then be read
to determine the specific condition that caused this bit to be set.
4 16
Message Available (MAV)
: A 1 in this bit position
indicates that the analyzer has data ready in the output queue.
There are no lower status groups that provide input to this bit.
5 32 Standard Event Status Summary Bit : A 1 in this bit
position indicates that the standard event status summary bit has
been set. The standard event status register can then be read to
determine the specific event that caused this bit to be set.
6 64 Request Service (RQS) Summery Bit : A 1 in this bit
position indicates that the analyzer has at least one reason to
report a status change. This bit is also called the master summary
status bit (MSS).
7 128
Operation Status Summary Bit
: A 1 in this bit position
indicates that the operation status summary bit has been set. The
operation status event register can then be read to determine the
specific event that caused this bit to be set.