
Register Descriptions
43
Read/Write Decoder
Lines Registers
Writing a value to one of these registers asserts the corresponding WP line.
Reading from one of these registers asserts the corresponding RP line. These
decoder lines can be used to expand the I/O registers. Refer to Chapter 2 for
timing information and using these registers.
Table 3-3 lists the Read/Write Decoder Register Addresses and the
corresponding WP and RP lines.
b+20
h -
b+2E
h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Write
Output Bits (BC15 - BC0)
Read
Input Bits (TR15 - TR0)
Table 3-3. Read/Write Decoder Lines and Register Addresses
WP / RP Line
Register Address
WP / RP Line
Register Address
WP0/ RP0
20
h
in A24 Memory
WP4 / RP4
28
h
in A24 Memory
WP1 / RP1
22
h
in A24 Memory
WP5 / RP5
2A
h
in A24 Memory
WP2 / RP2
24
h
in A24 Memory
WP6 / RP6
2C
h
in A24 Memory
WP3 / RP3
26
h
in A24 Memory
WP7 / RP7
2E
h
in A24 Memory
Содержание E2259A
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