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Getting Started  

17

to M-Module.

DREQ*:

Low to requests a DMA transfer, Output from 
M-Module.

DS0* - DS1*:

Data Strobe Signal, Input to M-Module
00 = 16 bit data transfer
01 = D15 - D08 transfer
10 = D7 - D0 transfer
11 = no data transfer.

DTACK*:

Data Acknowledge Signal, Output from M-Module. 
Low to acknowledge data transfer and terminate access.

IACK*:

Interrupt Acknowledge Signal, Input to M-Module. 
Low when interrupt is being acknowledged.

IRQ*:

Interrupt Request Signal, Output from M-Module. Low 
to request an interrupt.

RESET*:

System Reset Signal, Input to M-Module. Low to reset 
the module.

SYSCLK:

16MHz System Clock, Input to M-Module.

WRITE*:

Write Signal, Input to M-Module. Low during writing 
cycle, high during reading cycle.

Содержание E2259A

Страница 1: ...nt Service Center Repairs Experienced Engineers and Technicians on staff in our State of the art Full Service In House Service Center Facility InstraView Remote Inspection Remotely inspect equipment before purchasing with our Innovative InstraView website at http www instraview com We bUy used equipment We also offer credit for Buy Backs and Trade Ins Sell your excess underutilized and idle used e...

Страница 2: ...ed Programming This Manual Program Examples This Manual VISA language information Agilent VISA User s Guide Agilent VEE programming information Agilent VEE User s Manual Supplied with Agilent Command Modules Embedded Controllers and VXLink Agilent E2259A Double Wide Breadboard M Module User s Manual and Programming Guide Agilent M Modules E2259 90001 Manual Part Number E2259 90001 Printed in Malay...

Страница 3: ... ...

Страница 4: ... to Output Registers 20 Using the Write Decoder Lines 21 Reading Data From Input Registers 22 Using the Read Decoder Lines 23 Using the Interrupt 24 Program Example 25 Resetting the Module 28 Hardware Reset 28 Software Reset 28 Using the Power Supplies 28 Application Example 29 Relay Selection 29 Chapter 3 Register Descriptions 31 About This Chapter 31 Register Addressing in the VXIbus Environment...

Страница 5: ...2 Contents Appendix A Agilent E2259A Specifications 45 ...

Страница 6: ...tion or maintenance 7 TO THE EXTENT ALLOWED BY LOCAL LAW THE ABOVE WARRANTIES ARE EXCLUSIVE AND NO OTHER WARRANTY OR CONDITION WHETHER WRITTEN OR ORAL IS EXPRESSED OR IMPLIED AND AGILENT SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTY OR CONDITIONS OF MERCHANTABILITY SATISFACTORY QUALITY AND FITNESS FOR A PARTICULAR PURPOSE 8 Agilent will be liable for damage to tangible property per incident up to th...

Страница 7: ... equipment covers or shields Procedures involving the removal of covers or shields are for use by service trained personnel only Under certain conditions dangerous voltages may exist even with the equipment switched off To avoid dangerous electrical shock DO NOT perform procedures involving cover or shield removal unless you are qualified to do so DO NOT operate damaged equipment Whenever it is po...

Страница 8: ...EC 61000 4 3 1995 EN 61000 4 3 1995 IEC 61000 4 4 1995 EN 61000 4 4 1995 IEC 61000 4 5 1995 EN 61000 4 5 1995 IEC 61000 4 6 1996 EN 61000 4 6 1996 IEC 61000 4 11 1994 EN 61000 4 11 1994 Canada ICES 001 1998 Australia New Zealand AS NZS 2064 1 Limit Group 1 Class A 1 4kV CD 8kV AD 3 V m 80 1000 MHz 0 5kV signal lines 1kV power lines 0 5 kV line line 1 kV line ground 3V 0 15 80 MHz I cycle 100 Safet...

Страница 9: ...6 Notes ...

Страница 10: ...7 Notes ...

Страница 11: ...8 Notes ...

Страница 12: ...t E2259A Module Description The Agilent E2259A is a double wide breadboard M Module As a double wide module it occupies two adjacent slots in the Carrier However it is scored down the middle and can easily be snapped in half with all the active M Module interface circuits on one of the two halves See Figure 1 2 Even though the Agilent E2259A breadboard is a double wide in an Agilent E2251 Carrier ...

Страница 13: ...t The breadboard data input lines TR0 TR15 connect directly from the J103 pads to the U101 controller FPGA The data output lines BC0 BC15 are latched by U107 and U108 74ACTQ273SM and are available on J103 Control lines LAT DBEN CRST etc and the I O Decoder lines WP0 WP7 for write decoder lines and RP0 RP7 for read decoder lines are available on J102 Refer to Chapter 2 for information on using thes...

Страница 14: ...Getting Started 11 Figure 1 1 Agilent E2259A Block Diagram MA 7 0 MD 15 0 CS IACK WRIT E DS0 DS1 SYSCLK RESET DT ACK IRQ J100 Module Control ROM ID EEPROM ...

Страница 15: ...RD Only qualified service trained personnel aware of the hazards involved should install configure or remove the M Module Disconnect all power sources from the mainframe the terminal module and installed modules before installing or removing a module Caution VOLTAGE CURRENT Pay careful attention to the limitation of maximum voltage current and maximum power listed in Appendix A Exceeding any limit...

Страница 16: ...the buffered input and output lines read and write decoder lines busy line and power supply connections refer to J102 and J103 Pin Assignment on page 15 for detailed pinout Connectors J100 and J104 provide connections for user field wiring J100 directly maps pin for pin to access pads on J101 J104 maps pin for pin to access pads on J105 Figure 1 2 also shows the maximum component height above the ...

Страница 17: ...re for user field wiring J100 maps pin for pin to J101 see Figure 1 2 and J104 maps pin for pin maps to J105 Figure 1 3 shows the 44 pin field wiring connector pinout Figure 1 6 shows how to assemble the field wiring connector and hood assembly Figure 1 3 44 Pin Field Wiring Connector ...

Страница 18: ...elay Time Reg Addr 12h in A24 output from breadboard CINT Clear Interrupt A negative pulse is asserted during interrupt acknowledge if external interrupt request is pending output from breadboard EINT User Supplied External Interrupt Request Falling edge causes interrupt to host controller if enabled LAT Latch signal for write cycle output from breadboard CRST Reset low means breadboard being rese...

Страница 19: ...ct Signal Input to M Module Low when the M Module is being accessed MD00 to MD15 M Module Data Bus Input Output DACK Low when carrier is performing a DMA transfer Input Figure 1 5 P100 P101 P102 Connectors Pin Col A Col B 1 CS Ground 2 MA01 5V 3 MA02 12V 4 MA03 12V 5 MA04 Ground 6 MA05 DREQ 7 MA06 DACK 8 MA07 Ground 9 MD08 MD00 10 MD09 MD01 11 MD10 MD02 12 MD11 MD03 13 MD12 MD04 14 MD13 MD05 15 MD...

Страница 20: ... Output from M Module Low to acknowledge data transfer and terminate access IACK Interrupt Acknowledge Signal Input to M Module Low when interrupt is being acknowledged IRQ Interrupt Request Signal Output from M Module Low to request an interrupt RESET System Reset Signal Input to M Module Low to reset the module SYSCLK 16MHz System Clock Input to M Module WRITE Write Signal Input to M Module Low ...

Страница 21: ...the connector and hood Figure 1 6 Assembling the Field Wiring Connector and Hood 1 If necessary disassemble the connector hood Discard the three self tapping screws supplied with the hood 2 Release the latch on the side of the hood 3 Assemble bezel and cable clamp before wiring cable to connector 4 Use 24 AWG or smaller stranded wire Strip wires 1 8 6 Assemble connector using supplied machine scre...

Страница 22: ...gister Address Register Description VXI ID Register 00h in VXI A16 Memory Provides Device Class and Manufacturer ID VXI Device Type Register 02h in VXI A16 Memory Provides Model Code for M Module VXI Status Control Register 04h in VXI A16 Memory Controls Reset and Provides module Status information A24 Offset Register 06h in VXI A16 Memory Provides A24 Offset Base Address Interrupt Selection Regis...

Страница 23: ...ce information only Note W14 has the same timing as LAT when writing to 14H in A24 memory space IRQ is asserted at the end of the BUSY cycle see Using the Interrupt on page 24 The BUSY line pulse lasts 13mS if the module default is used You can change the BUSY time by writing a value to the Delay Timer Register at address 12h Refer to Chapter 3 for details MD15 MD0 are latched to BC15 BC0 at the r...

Страница 24: ...riting to addresses other than14H in A24 memory space MD15 MD0 are latched to latches on the rising edge of WPn Figure 2 2 shows an example of using the WP0 Decoder Line to serve as a device latch signal To create an expanded register write a data value to the appropriate Read Write Decoder Register For example to use the circuit in Figure 2 2 you would write a 16 bit data value to the WP0 registe...

Страница 25: ...lustrates the timing required for reading data from this register on the Agilent E2259A Breadboard You only have access to the DBEN and LAT control lines the other control line waveforms are provided for reference information only Figure 2 3 Timing of Reading Data from Registers MSYSCLK DS0 DS1 CS DTACK MA 7 0 MD 15 0 RPn 16MHz 62 5 ns 62 5 ns 62 5 ns 190 ns 40 ns 62 5 ns DBEN LAT ...

Страница 26: ... as select lines to specify which device the data is read from Figure 2 3 also shows the timing of the RPn pulse Table 2 3 lists the Read Write Decoder Register Addresses and the corresponding WP and RP lines Table 2 3 Read Write Decoder Lines and Register Addresses WP RP Line Register Address WP RP Line Register Address WP0 RP0 20h in A24 Memory WP4 RP4 28h in A24 Memory WP1 RP1 22h in A24 Memory...

Страница 27: ...ading the Interrupt Register will clear the interrupt request signal IRQ to support Type A interrupt Bits 2 through bit 15 of this register are not used Bit 1 indicates an external interrupt existing if the content of bit 1 is 1 See Chapter 3 Register Description for more information of this Interrupt Register IRQ will be valid whenever the external interrupt occurs Figure 2 4 shows the timing for...

Страница 28: ...set the Agilent E2259A Breadboard M Module It then Reads the ID Device Type Status and A24 Memory Offset Registers Writes a value to the I O Register to output data on BC0 BC15 Writes a value to the WP0 Register to output data on BC0 BC15 Reads a value from the I O Register to input data on TR0 TR15 Reads a value from the RP0 Register to input data on TR0 TR15 include visa h include stdio h includ...

Страница 29: ...tatus register 0x hx n stat_reg read and print the module s A24 Offset Register errStatus viIn16 m_mod VI_A16_SPACE 0x06 a24_offset if VI_SUCCESS errStatus printf ERROR viOpen returned 0x x n errStatus return errStatus printf A24 Offset register value 0x hx n a24_offset Write a value of AA to I O Register Addr 0x14 errStatus viOut16 m_mod VI_A24_SPACE 0x14 0xAA if VI_SUCCESS errStatus printf ERROR...

Страница 30: ...x x n errStatus return errStatus printf 0x20 register value 0x hx n value Close the M Module Instrument Session errStatus viClose m_mod if VI_SUCCESS errStatus printf ERROR viClose returned 0x x n errStatus return 0 Close the Resource Manager Session errStatus viClose viRM if VI_SUCCESS errStatus printf ERROR viClose returned 0x x n errStatus return 0 return VI_SUCCESS ...

Страница 31: ...le for use by external circuits is protected by a positive temperature coefficient thermistor When maximum current through the thermistor is reached it heats up and its resistance increases significantly thereby limiting the current the thermistor acts like a resettable fuse Table 2 4 lists the power supplies thermistor protection reference designator silkscreened on PC board and the maximum curre...

Страница 32: ...sed as the interface To open one specific relay you need to WRITE a 0 to the bit of the I O Register which corresponds to that relay To close a channel you need to write a 1 to the corresponding I O Register bit Figure 2 5 Write a 1 or 0 to the Register Bit to Close Open the Relay The status of all relays must be specified simultaneously To change just one relay it is necessary to change the corre...

Страница 33: ... SET DS2E S DC12V K407 1 2 3 4 5 6 7 8 REL0 12VB C00 NC00 NO00 COM COM RST RST SET SET DS2E S DC12V K400 1 2 3 4 5 6 7 8 REL2 12VB C02 NC02 NO02 COM COM RST RST SET SET DS2E S DC12V K402 1 2 3 4 5 6 7 8 REL1 12VB C01 NC01 NO01 COM COM RST RST SET SET DS2E S DC12V K401 1 2 3 4 5 6 7 8 REL3 12VB C03 NC03 NO03 COM COM RST RST SET SET DS2E S DC12V K403 BC 15 0 BC0 BC1 BC2 BC3 BC4 BC5 BC6 BC7 REL0 REL1...

Страница 34: ...E2251 Installation and Getting Started Guide for details if you are using a different carrier refer to that carrier s documentation for register based addressing information A16 A24 Memory Mapping The VXI Specification allows for only 64 bytes of address space in A16 memory However the M Module Specification defines 256 bytes of address space To resolve this conflict the Agilent E2251 Carrier prov...

Страница 35: ...l address Figure 3 1 A16 A24 Memory Mapping A16 Address Map 20 2Eh 14h 12h 04h 02h 00h 20h 00h 02h 04h 06h A24 Address Map ID Register Device T ype Register Status Control Register Offset Register Interrupt Control Register Delay Register Interrupt Register Control Register StatusRegister Base Address 1FC000 Logical Address 64 or 2 080 768 Logical Address 64 A16 Register Address Base Address Regis...

Страница 36: ...00h or decimal 49 152 120 64 49 152 7680 56 832 Addressing A16 Registers As shown in Figure 3 1 VXI registers for an M Module are mapped into A16 address space by the Agilent E2251 Carrier To access one of these registers add the A16 base address to the register offset For example an M Module s VXI Status Control Register has an offset of 04h To access this register assuming the system does not ha...

Страница 37: ...34 Register Descriptions or decimal 2 097 408 16 2 097 424 ...

Страница 38: ...Status from each VISA call session Open the default resource manager errStatus viOpenDefaultRM viRM if VI_SUCCESS errStatus printf ERROR viOpenDefaultRM returned 0x x n errStatus return errStatus Open the M Module instrument session errStatus viOpen viRM INSTR_ADDR VI_NULL VI_NULL m_mod if VI_SUCCESS errStatus printf ERROR viOpen returned 0x x n errStatus return errStatus read and print the module...

Страница 39: ...A24_SPACE 0x12 0x1D6 if VI_SUCCESS errStatus printf ERROR viOut16 returned 0x x n errStatus return errStatus Output a Value of 5 on BCn Data Lines errStatus viOut16 m_mod VI_A24_SPACE 0x14 0x05 if VI_SUCCESS errStatus printf ERROR viOut16 returned 0x x n errStatus return errStatus Close the M Module Instrument Session err_status viClose m_mod if VI_SUCCESS errStatus printf ERROR viClose returned 0...

Страница 40: ...tion information Device Class this bit should always be 11 indicating a register based device Address Space 00 indicating A16 A24 device Manufacturer ID 4095 decimal for Agilent Technologies M Modules VXI Device Type Register The Device Type Register is a read only register at address 02h Reading this register returns a unique identifier for each M Module Required Memory Fh indicating 256 byte blo...

Страница 41: ... on the P2 MODID line Ready A 1 in this bit indicates that the M Module is ready to accept commands A 0 indicates the M Module is busy and not ready to accept commands Passed A 1 in this bit indicates the M Module passed its self test successfully A 0 indicates the M Module is either executing or has failed its self test VXI Offset Register The Offset Register address 06h contains the value of the...

Страница 42: ...tion instructs you to change the interrupt level you need to specify the level in the VXI Interrupt Selection Register To cause the M Module to interrupt on one of the VXI interrupt lines write to the appropriate bits refer to table below To disable the module s interrupt set the bits to 000 Selecting other than the default interrupt line 1 is not recommended Reading the default value of this regi...

Страница 43: ...fications however only two types of interrupts are defined RORA Release on Register Access and ROAK Release on Acknowledge The Agilent E2251A Carrier converts M Module Type A interrupts to RORA and Types B and C interrupts to ROAK default RORA Interrupts The interrupting device provides its logical address on the data bus MD0 MD7 during the interrupt acknowledge cycle that was initiated in respons...

Страница 44: ...ists the address mapping A24 Status Register The offset of Status Register is 00h It is a Read only register BUSY 0 Circuit is busy not stable yet EIRQX 1 External interrupt RIRQX 1 Circuit interrupt Table 3 2 Agilent E2259A Registers in A24 Memory Address Registers FEh EEPROM 30h FCh Reserved 20h 2Eh Read Write Decoder Registers 16h 1Eh Reserved 14h I O Register 12h Delay Register 10h Reserved 06...

Страница 45: ...ution and asserting interrupt The delay time is determined by the formula Delay Time Register value 1 0 031875 ms where Register value can be from 0000h through FFFFh The default value of Delay Time is 13 ms register value 40710 or 197h I O Register The offset of the Input Output Register is 14h Reading this Register will get the status of TR0 TR15 lines Writing to this Register will latch MD15 MD...

Страница 46: ...gisters Table 3 3 lists the Read Write Decoder Register Addresses and the corresponding WP and RP lines b 20h b 2Eh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Write Output Bits BC15 BC0 Read Input Bits TR15 TR0 Table 3 3 Read Write Decoder Lines and Register Addresses WP RP Line Register Address WP RP Line Register Address WP0 RP0 20h in A24 Memory WP4 RP4 28h in A24 Memory WP1 RP1 22h in A24 Memory WP...

Страница 47: ...st 16 words 0 through 15 are defined in the M Module Specifications words 16 63 are described in Table 3 4 Table 3 4 EEPROM Contents Word Description Value 0 Sync code 5346h 1 module number binary code 1659h 2 revision number binary code 0001 3 module characteristics 1868h 4 7 reserved 8 15 User defined 16 VXI Sync code ACBAh 2 s complement of 0x5346 17 VXI ID CFFFh 18 VXI Device Type F258h 19 31 ...

Страница 48: ...Diameter 1 17 mm 0 046 in Maximum Component Height 5 3 mm 0 21 in above board in Region A 10 5 mm 0 42 in above board in Region B Refer to Agilent E2259A Connectors Layout on page 13 Maximum Lead Length 1 2 mm 0 078 in below board Refer to Agilent E2259A Connectors Layout on page 13 Maximum Power Dissipation per module Determined by mainframe cooling and or Agilent E2251A Cooling Capacity Do not e...

Страница 49: ...46 Agilent E2259A Specifications ...

Страница 50: ...rol Register A24 42 CS 16 D D00 to D15 16 DACK 16 Decoder Lines 21 Decoder Lines Register 43 Delay TImer Register 42 Description Module 9 Device Type Register 37 DREQ 17 DS0 DS1 17 DTACK 17 E EEPROM 10 44 EEPROM Words 44 Example Application 29 Program 25 F Features 9 G General Features 9 I I O Decoder Lines Register 43 IACK 17 24 ID EEPROM 10 44 ID Register 37 Input Circuit 10 Input Registers 22 I...

Страница 51: ...atus 41 BUSY Delay Timer 42 Device Type 37 I O Decoder Lines 43 ID 37 Interrupt Selection 39 Status Control 38 Register Addressing 31 Registers 19 RESET 17 Resetting the Module 28 Restrictions Component height 13 S Specifications 45 Status Register A24 41 Status Control Register 38 SYSCLK 17 V VXI A24 Offset Register 38 VXI Device Type Register 37 VXI ID Register 37 VXI Status Control Register 38 ...

Страница 52: ...nt Service Center Repairs Experienced Engineers and Technicians on staff in our State of the art Full Service In House Service Center Facility InstraView Remote Inspection Remotely inspect equipment before purchasing with our Innovative InstraView website at http www instraview com We bUy used equipment We also offer credit for Buy Backs and Trade Ins Sell your excess underutilized and idle used e...

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