Understanding the Agilent E1330B Digital I/O Module
43
Chapter 4
The STS Line
Each port has a status line labeled STS. The STS line is an input line to the
Digital I/O module. The use of the STS line is only at the register level, and
is not supported by SCPI commands. Refer to Appendix B for more
information about this line.
The PIR Line
Each port has a peripheral interrupt request line labeled PIR. The PIR line is
an input line to the Digital I/O module. The use of the PIR line is only at the
register level, and is not supported by SCPI commands. Refer to Appendix
B for more information about this line.
The RES Line
Each port has a reset line labeled RES. The RES line is an open collector
output line to the peripheral. Control of the RES line is only at the register
level and is not supported by SCPI commands. Refer to Appendix B for
more information about this line.
Default and Reset States
At initial power-on and following the
*RST
command, the Digital I/O
module is set to the following states:
Setting the Polarity
The logical true level of the control (CTL) line, the flag (FLG) line, and the
data lines of each port can be set to either TTL high (>2.5V) or TTL Low
(< 1.4V) levels. SCPI commands use the POLarity keyword as:
[SOURce:]DIGital:CONTrol
n
:POLarity <POSitive
or
NEGative>
to set the control line's (CTL) polarity on port n.
[SOURce:]DIGital:FLAG
n
:POLarity <POSitive
or
NEGative>
to set the flag line's (FLG) polarity on port n.
[SOURce:]DIGital:DATA
n
:POLarity <POSitive
or
NEGative>
to set the data lines polarity on port n.
Example
DIG:DATA1:POL POS
Sets the polarity to positive on port 1 data lines, a TTL high will be input as
a 1, or a bit set to 1 will output a TTL High level.
The
*RST
(reset) condition is positive polarity for control (CTL),
flag (FLG), and data lines on all ports.
CTL line:
0 = TTL Low
I/O line:
TRUE = input = TTL High
Data, FLG, and CTL line Polarity:
POSitive
Handshake mode:
NONE
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