Advantech MIC-5332, Руководство пользователя

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Figure 4.1 IPMC Interface Block Diagram
4.2.1.1 IPMB-0 Interface
The IPMB0 interface is the communication path between the ShMC and IPMC
through Zone 1. Two–way redundant IPMB-0 channels (IPMB0-A and IPMB0-B)
provide immunity against failures of one of IPMB-0 channels.
For a request received over IPMB0-A, the response will be sent over IPMB0-B. Any
requests that time out are retried on the redundant IPMB bus. The IPMC monitors the
bus for any link failure and isolates itself from the bus if an error is detected.
The IPMB address of IPMC is determined by Hardware Address pins (HA[7:0]) on the
Zone 1 connector. The manual of the chassis/backplane contains information that
allows relating the physical IPMB address to the slot location within the chassis.
4.2.1.2 IPMB-L Interface
IPMB-L is the interface between the IPMC and a Module Management Controller
(MMC) on a compliant RTM such as the RTM-5104. It is connected to the IPMB-L bus
through I
2
C bus isolators.
4.2.1.3 System Interface
The x86 subsystem (referred to as payload) may communicate with the IPMC via a
KCS interface. The KCS commands will be transferred through a Low Pin Count (LPC)
interface between the Patsburg-B PCH and the IPMC.
4.2.1.4 LAN (NC-SI) Interface
The Intel i350-AM4 controller provides a sideband interface (NC-SI) that can be used
by the IPMC. Serial-over-LAN (SoL) uses the RMCP+ protocol over this interface to
encapsulate serial data in network packets and pass them between the payload and
the remote console. IPMI over LAN (IoL) may be used to communicate with the IPMC
over the BI or IO Ethernet LAN ports connected to the i350-AM4.