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VSBC-6862

Rev 1.43

52

48T37V partial register map is:

Base +

D7

D6

D5

D4

D3

D2

D1

D0

Function (Range) BCD format

$7FFF

10 Years

Year

Year (00-99)

$7FFE

0 0 0

10M.

Month

Month

(01-12)

$7FFD

0

0

10 Date

Date

Date (01-31)

$7FFC

0 FT 0 0 0

Day

Century/Day

(0-1/01-07)

$7FFB

0

0

10 Hours

Hours

Hour (00-23)

$7FFA

0

10 Minutes

Minutes

Minutes (00-59)

$7FF9

ST

10 Seconds

Seconds

Seconds (00-59)

$7FF8 W R S

Calibration

Control

$7FF7 WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0

Watchdog

$7FF6

AFE

0

ABE

0 0 0 0 0

Interrupts

$7FF5

RPT4

0

Alarm 10 Date

Alarm Date

Alarm Date (01-31)

$7FF4

RPT3

0

Alarm 10 Hours

Alarm Hours

Alarm Hours (00-23)

$7FF3

RPT2

Alarm 10 Minutes

Alarm Minutes

Alarm Minutes (00-59)

$7FF2

RPT1

Alarm 10 Second

Alarm Seconds

Alarm Seconds (00-59)

$7FF1

1000 Years

100 Years

Century

$7FF0 WDF AF

Z

BL

Z

Z

Z

Z

Flags

With:

S = sign bit

AF = Alarm Flag

FT = Frequency Test bit

BL = Battery Low Flag

R = Read Bit

WDS = Watchdog Steering Bit

W = Write Bit

BMB0-BMB4 = Watchdog Multiplier Bits

ST = Stop Bit

RB0-RB1 = Watchdog Resolution Bits

0 = Must be set to ’0’

AFE = Alarm Flag Enable

Z = ’0’ and are Read only

ABE = Alarm in Battery Back-up Mode Enable

WDS = Watchdog Steering Bit

RPT1-RPT4 = Alarm Repeat Mode Bits

WDF = Watchdog Flag

4.5.1. RTC registers read operation

The RTC registers are continuously updated by the device.
Updates to the RTC registers should be halted before clock data is read to prevent reading data in
transition.
Because the registers are only copy of the clock counters, updating the registers can be halted without
disturbing the clock itself. Updating is halted when a ’1’ is written to the READ bit, D6 in the Control
Register 7FF8h. As long as a ’1’ remains in that position, updating is halted. After a halt is issued, the
registers reflect the count; that is, the day, date, and the time that was current at the moment the halt
command was issued. All of the RTC registers are updated simultaneously. A halt will not interrupt an
update in progress. Updating is within a second after the bit is reset to a ’0’.

4.5.2. RTC registers write operation

Bit D7 of the Control Register 7FF8h is the WRITE bit. Setting the WRITE bit to a ’1’, like the READ
bit, halts updates to the RTC registers. The user can then load them with the correct day, date, and
time data in 24 hour BCD format. Resetting the WRITE bit to a ’0’ then transfers the values of all time
registers 7FF9h-7FFFh to the actual RTC counters and allows normal operation to resume. After the
WRITE bit is reset, the next clock update will occur in approximately one second.

See the ST Microelectronics Application Note AN923 "TIMEKEEPER rolling into
the 21st century" on the ST Web site for information on Century Rollover.

Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com

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Содержание VSBC-6862

Страница 1: ...service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE IN...

Страница 2: ...Single Board Computer with PowerQUICC II processor Revision 1 43 3105 ACTIS Computer www actis computer com support actis computer com Artisan Technology Group Quality Instrumentation Guaranteed 888 8...

Страница 3: ...VSBC 6862 Rev 1 43 2 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Страница 4: ...__________________ 23 3 2 Rotary switch SW1______________________________________________________ 23 3 3 IP module strobes header J1 ______________________________________________ 24 3 4 Jumper J2 ___...

Страница 5: ...orts ___________________________________________________ 70 4 9 3 Transceivers operations ________________________________________________ 71 4 10 SMC1 and SMC2 serial ports __________________________...

Страница 6: ...____________________ 120 10 5 Other________________________________________________________________ 120 11 Hardware available___________________________________________________ 121 11 1 List of ACTIS...

Страница 7: ...e 25 Application example with non VME boards 132 Figure 26 Application example in stand alone 133 For up to date documentation please refer also to our web site at http www actis computer com While ef...

Страница 8: ...itecture is more efficient than traditional architectures because the CPM offloads peripheral tasks from the embedded PowerPC core This single board computer in 6U form factor is VME bus master and sl...

Страница 9: ...bles banks one bank dual port with the VME bus 1 MByte of SRAM memory dual port with the VME bus Non volatile operation through the VME stand by signal A separate real time clock device with 32 kByte...

Страница 10: ...de 9 1 3 Photograph Figure 1 Photograph The VMEbus Technology logo is a Trademark of the VMEbus International Trade Association Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURC...

Страница 11: ...is section handles all internal board logic like board registers plus the handling of IP modules and VME functions The I O section This section is the external part of the PowerQUICC II I O ports it c...

Страница 12: ...Rev 1 43 User s Guide 11 1 5 Component location Figure 3 Component location Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Страница 13: ...avoid problems of component availability either for debug purposes From the user side its totally transparent nothing has to be modified For special uses that need a precise component implementation...

Страница 14: ...ls thus inverting the bootable Flash memory bank One Flash memory bank is also shared with the VME bus This permits an external master to reprogram the VSBC 6862 Firmware or use this memory as non vol...

Страница 15: ...device is also accessible from the VME bus Note The SNAPHAT housing plugged on the M48T37V contains both battery and crystal Thus for the minimum frequency error the user has to calibrate the RTC in...

Страница 16: ...I O spaces These features can be divided in three functions General board functions Two registers are used to generate Reset on the board and to read the rotary switch value IP functions Each of the...

Страница 17: ...L register Depending of the IRQ level to be acknowledged the user can read the vector in the corresponding offset in the VHV register When reading the vector the interrupt acknowledge cycle is initiat...

Страница 18: ...ure automatically selects internal 10Base T or 100Base TX full or half duplex as a result of negotiation between the station and its link partner The SMSC LAN83C183 supports half and full duplex opera...

Страница 19: ...CD All ports support hardware handshaking and synchronous functions DSR signals are pulled up to VCC to indicate that the board is powered up RS 422 RS 485 V 35 modes These VSBC 6862 ports are compati...

Страница 20: ...nt panel These indicators have to be handled by the user These two LEDs are active low The following table provides the relation between the front panel LED s and their corresponding condition sources...

Страница 21: ...VSBC 6862 Rev 1 43 20 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Страница 22: ...upwards the first connectors for IP serial ports and Fast Ethernet ports are in the bottom of the board Behind each serial port are the corresponding termination resistors and jumpers Pin numbering c...

Страница 23: ...VSBC 6862 Rev 1 43 22 Locations Figure 4 Connectors and jumpers location Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Страница 24: ...ush Button was generating a Hardware Reset instead of Power On Reset 3 2 Rotary switch SW1 The eight position rotary switch is a facility provided for user purposes This switch can be used for example...

Страница 25: ...pers permit to access or connect pull downs to these signals These jumpers are located near P2 Figure 7 Jumper J1 location The pins are assigned as follows Pin Signal Description 1 Strobe A Strobe for...

Страница 26: ...n Plugged in The RSTCONF pin is at VCC Description This jumper is used to force the PowerQUICC II to use the default ResetWord The main usage of this jumper is to boot the board for the first time bef...

Страница 27: ...will generate a board Hardware Reset Position 6 VME Slot1 function Factory setting Description Unplugged X The VME Slot1 functions are disabled Plugged in The VME Slot1 functions are enabled Descript...

Страница 28: ...erial port SCC1 J5 correspond to serial port SCC2 J6 correspond to serial port SCC3 J7 correspond to serial port SCC4 For RS 232 protocols set all six jumpers in RS 232 position 1 2 4 5 7 8 10 11 13 1...

Страница 29: ...ugged represents an address line in the state 0 with position 1 VME address A11 position 2 VME address A12 position 3 VME address A13 position 4 VME address A14 position 5 VME address A15 Example Figu...

Страница 30: ...e ports are handled by the SMC1 and SMC2 functions of the PowerQUICC II processor P13 is available on the front panel with an RJ 45 connector defined as following Figure 13 Connector P13 pinout Pin Si...

Страница 31: ...HE 10 connector defined as following Figure 14 Connector P4 pinout Pin Signal Description 1 n u Not used 2 3 3V 3 3 V 500mA fuse 3 5V 5 0 V 500mA fuse 4 n u Not used 5 GND GND 6 GND GND 7 I2CSCL I2 C...

Страница 32: ...nsmit Data 3 TxD Out n u Transmit Data 4 TxC Out Transmit Clock Transmit Clock 5 TxC Out n u Transmit Clock 6 RTS Out Request To Send Request To Send 7 GND Ground Ground 8 CTS In Clear To Send Clear T...

Страница 33: ...or network is located as RZ34 RZ35 port SCC 1 RZ36 RZ37 port SCC 2 RZ38 RZ39 port SCC 3 RZ40 RZ41 port SCC 4 Note that the pins 1 of these removable networks are in opposed side than the already solde...

Страница 34: ...nnector P11 corresponds to FCC1 Figure 17 Fast Ethernet ports pinout Pin Signal Description 1 TxD Transmit data positive output 2 TxD Transmit data negative output 3 RxD Receive data positive input 4...

Страница 35: ...ard This connector definition complies with the industry standard definition for its assignment Figure 18 JTAG port pinout Pin Signal Description 1 TDO Serial output data 2 3 3V 3 3V max 0 3 mA 3 TDI...

Страница 36: ...A14 WRITE B14 BR2 C14 AM5 A15 GND B15 BR3 C15 A23 A16 DTACK B16 AM0 C16 A22 A17 GND B17 AM1 C17 A21 A18 AS B18 AM2 C18 A20 A19 GND B19 AM3 C19 A19 A20 IACK B20 GND C20 A18 A21 IACKIN B21 C21 A17 A22 I...

Страница 37: ...IP D I O 24 B12 GND C12 IP D I O 23 A13 IP D I O 26 B13 5 V C13 IP D I O 25 A14 IP D I O 28 B14 D16 C14 IP D I O 27 A15 IP D I O 30 B15 D17 C15 IP D I O 29 A16 IP D I O 32 B16 D18 C16 IP D I O 31 A17...

Страница 38: ...sed for IP module slots GND Ground 5 V STDBY Power supply furnished by an non interruptible power source TM 5 V 5 V provided by the VSBC 6862 to an optional transition module Fuse protected This conne...

Страница 39: ...ector P3A IP slot D The following table gives the connectors assignment which refers to the VITA 4 specification Pin Signal Pin Signal 1 GND 26 GND 2 CLK 27 5 V 3 RESET 28 R W 4 D0 29 IDSEL 5 D1 30 DM...

Страница 40: ...gnment provides the straight connection from the IP module I O connector with ACTIS cable set reference CAB 85B Pin Signal Pin Signal 1 I OD 1 2 I OD 2 3 I OD 3 4 I OD 4 5 I OD 5 6 I OD 6 7 I OD 7 8 I...

Страница 41: ...operation caution must be taken in order to avoid hardware damage Please use the following instructions for the battery replacement 1 Turn the main power supply off 2 Remove the used battery located...

Страница 42: ...e the fuse will automatically break the circuit When it will be cold it becomes again normal Fuse Intensity Power supply F16 2A IP module A 5 V F15 2A IP module B 5 V F11 2A IP module C 5 V F12 2A IP...

Страница 43: ...VSBC 6862 Rev 1 43 42 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Страница 44: ...e IP and VME devices The error generation is mainly handled with the internal bus monitor included in the 8260 See the SYPCR register and bus monitor description in the 8260 User s manual Here follows...

Страница 45: ...onnected to this chip select must contain the Reset initialization Word for the PowerQUICC II and is boot code If the Reset Word is not valid the board can be started with a default Reset initializati...

Страница 46: ...trols the same device as CS0 it will have the same register values Typical Base Register BR2 zzzz 1801 Typical Option Register OR2 FFC0 0068 Once these Chip Select registers are configured access to t...

Страница 47: ...erase architecture The sector erase mode allows for sectors of memory to be erased and reprogrammed without affecting other sectors A sector is typically erased and verified within 1 second if already...

Страница 48: ...64 kword 64 kword 64 kword 27 64 kword 64 kword 64 kword 64 kword 28 64 kword 64 kword 64 kword 64 kword 29 64 kword 64 kword 64 kword 64 kword 30 64 kword 64 kword 64 kword 64 kword 31 64 kword 64 kw...

Страница 49: ...configured with its own set of registers as OR1 BR1 PSDMR The SDRAM device is configured by accessing the PSDMR register in a specific manner Here follows the full description to initialize the SDRAM...

Страница 50: ...C 100 Refresh recovery 4 clocks 17 19 PRETOACT 010 Precharge to activate interval 2 clocks 20 22 ACTTORW 010 Activate to Read Write interval 2 clocks 23 BL 0 Burst length for 64 bits 24 25 LDOTOPRE 01...

Страница 51: ...0 Data error correction off 23 WP 0 Write protect off 24 26 MS 000 Machine select GPCM on 60x bus 27 EMEMC 0 External mem cntrl enable off 28 29 ATOM 00 Atomic operation off 30 DR 0 Data pipelining no...

Страница 52: ...n 0 16 BA xxxxb Base address user defined 17 18 Reserved 00 19 20 PS 01 Port size 8 bits 21 22 DECC 00 Data error correction off 23 WP 0 Write protect off 24 26 MS 000 Machine select GPCM on 60x bus 2...

Страница 53: ...vice Updates to the RTC registers should be halted before clock data is read to prevent reading data in transition Because the registers are only copy of the clock counters updating the registers can...

Страница 54: ...1 in the SRESR register Once activated this connection can not be disabled until next Power On Reset In this case when the Watchdog s counter reachs zero the VSBC 6862 will be completely Resetted The...

Страница 55: ...d internal resynchronizations the IP clock has been defined as derived from the bus clock 66MHz This permits the logic to be more efficient in terms of speed Thus the IP clock is not VITA 4 compliant...

Страница 56: ...lid bit on BR4 xxxx 1081 Typical Option Register Bit Field Value Function 0 16 AM FFFF 1 Address mask for 32 kBytes 17 18 Reserved 00 19 BCTLD 0 Buffer control on 20 22 Reserved 000 23 Burst inhibit 1...

Страница 57: ...will be resumed as Description Example Set the Base Register BR4 0xfa001081 Set the Option Register OR4 0xffff8100 Set the MxMR to write at offset 0 for Single Read MAMR 0x10040000 Set the MDR with t...

Страница 58: ...have the four IP slots fully independent These registers are controlled by the Chip Select 4 For detailed register description please see the chapter Register Description Partial Chip Select 4 memory...

Страница 59: ...gic provides specific function in order for ensuring interrupt acknowledge compatibility The process becomes as follows 1 An interrupt request is generated by the IP module 2 If the GCRx ENIRQ bit is...

Страница 60: ...by IDMA1 Slot B controlled by IDMA2 Slot C controlled by IDMA3 The DMA signals are assigned on the PowerQUICC II as the following table MPC 8260 Peripheral function I O Function I O Signal Descriptio...

Страница 61: ...egister This register permits to generate by software Reset signals to the board Resets can be initiated to the MPC8260 board peripherals and Flash memory It permits also to connect the external RTC s...

Страница 62: ...isters The VSBC 6862 contains registers to configure the VME operations These registers are controlled by the Chip Select 4 Partial Chip Select 4 memory map and VME A16 slave map CS4 Offset Slave offs...

Страница 63: ...matically set with the corresponding value to indicate the address mode used The AM0 to AM2 bits are user definable with the VMAMx registers The selection for D8 D16 and D32 are made dynamically with...

Страница 64: ...the usage of sharable memory It is called pseudo RMW cycle because it does not comply with the VME standard RMW definition but it can achieve the same result This function is available through the VSB...

Страница 65: ...ter accesses the local SRAM Moreover an external master can access the VSBC 6862 while it is not initialized All slave functions are independent of the MPC 8260 state These zones are divided in two wi...

Страница 66: ...56kB 32kB slave window 1MB 16MB Flash bank 8MB VSWA24 FLAx VSWA24 SRAx Figure 20 VME slave window The bootable Flash memory bank 0 is 8 MBytes the VME slave window for Flash is 256 kBytes 32 positions...

Страница 67: ...the interrupt level and the vector must be defined with the VIVEC register The corresponding interrupt signal is activated when writing any value to the VINTER register This interrupt stay active unti...

Страница 68: ...driver 16 MHz system clock generator 4 7 9 Specific features for VME Jumpers can modify the links between VME reset and VSBC 6862 reset as When the VME_Reset_In jumper is plugged and if the board is...

Страница 69: ...es they will generally contains some boards specific information like physical Ethernet addresses Please see the chapter Board initialization for more details The chip used is a M24C08 and is configur...

Страница 70: ...plex operation at both 10Mbps and 100Mbps speeds It complies with ANSI X3T9 TP PMD and includes MLT 3 Encoder Decoder and Stream Cipher scrambler de scrambler functions for 100Base TX The SMSC LAN83C1...

Страница 71: ...data PB19 MII_RXD2 I ECRXD2 receive data PB20 MII_RXD1 I ECRXD1 receive data PB21 MII_RXD0 I ECRXD0 receive data PC4 MII_IRQ2 I MII_IRQ2 irq Fast Ethernet port 2 PB4 MII_MDC O ECMDC data clock PB5 MI...

Страница 72: ...t with the following two step sequence especially during initialization time Reset PHY by writing 8000h to PHY register 0 Poll bit 15 Reset in PHY register 0 until it is 0 for the reset completion Tim...

Страница 73: ...eserved Reserved RO 0 6 MF Preambule suppression 1 accept management frames with short preamble 0 normal preamble only RO 0 5 Auto negotiation compl 1 auto negotiation process complete 0 auto negotiat...

Страница 74: ...n 0 not capable RO 1 PHY register address 17 Structure and Bit definition Bit NAME DESCRIPTION R W DEFAULT 15 14 Programmable LED output 3 11 normal 10 LED blink 01 LED on 00 LED off R W 11 13 12 Prog...

Страница 75: ...Activity Link 100Mb s Activity Full Duplex Link 10 Mb s The RJ 45 green LED for the link indication is connected to the LED_3 signal The RJ 45 yellow LED for the activity indication is connected to th...

Страница 76: ...I RxD Receive data For related software setup please refer to the corresponding Motorola MPC 8260 user s manual and application notes 4 10 2 ACTIS Console Cable ACTIS can provide a serial cable for th...

Страница 77: ...h the protocolx jumpers The serial ports 1 and 3 have an added function they can be internally used to synchronize the internal Baud Rate Generators BRG with external clock signal 4 11 1 RS 232 option...

Страница 78: ...TS as normal RTS The PowerQUICC II has also the possibility to disable his receiver while emitting see bit DRT in register PSMR Each port has its own resistor network These resistors are on sockets AC...

Страница 79: ...e Length 1 8m Pinout Pin function RS 232 V 35 Sub D 15 3 rows male Sub D 25 2 rows male Shield Shield 1 1 TxD TxD 2 2 RxD RxD 14 3 RTS RTS 6 4 CTS CTS 8 5 DSR DSR 15 6 GND GND 7 7 DCD DCD 10 8 Not use...

Страница 80: ...I DCD Data carrier detect PD17 BRG2 O TxC Transmit clock PC28 CLK4 I RxC Receive clock SCC3 PB8 TXD3 O TxD Transmit data PB14 RXD3 I RxD Receive data PD23 RTS3 O RTS Request to send PC11 CTS3 I CTS C...

Страница 81: ...nction I O Function I O Signal Description I2C PD14 I2CSCL O I2CSCL clock PD15 I2CSDA I O I2CSDA data For related software setup please refer to the corresponding Motorola MPC 8260 user s manual and a...

Страница 82: ...on Register 681 IPIVRC RO IP C Interrupt Vector 701 IPGCRD RW IP D General Configuration Register 703 IPDCRD RW IP D DMA Configuration Register 781 IPIVRD RO IP D Interrupt Vector 1001 9 SRESR WO Soft...

Страница 83: ...QUICC II I O ports as Fast Ethernet controller 1 I O port C6 Fast Ethernet controller 2 I O port C4 The Real Time Clock is also able to generate an IRQ This line is connected as RTC IRQ I O port C5 Al...

Страница 84: ...ic jumper is installed The HRESET can be generated by a specific write operation in register of programmable logic the P3 connector and is sent to the PowerQUICC II all board s devices excepted the pr...

Страница 85: ...protected A power fail logic monitors if the 5V voltages are present on the IP slots If one of these voltages is not detected the PowerLed on front panel is then OFF You have to check the cause of the...

Страница 86: ...C31 BRG1 O TxC Transmit clock PC29 CLK3 I RxC Receive clock SCC2 PB12 TXD2 O TxD Transmit data PB15 RXD2 I RxD Receive data PD26 RTS2 O RTS Request to send PC13 CTS2 I CTS Clear to send PA23 PA23 O DT...

Страница 87: ...irq Fast Ethernet port 2 PB4 MII_MDC O ECMDC data clock PB5 MII_MDIO I O MIIMDIO data PA30 MII_CRS I MIICRS carrier sense PA31 MII_COL I MIICOL collision PA28 MII_TX_EN O MIITXEN transmission enable...

Страница 88: ...I O DMADONE2 IDMA done PA1 IDMA3 DONE I O DMADONE3 IDMA done PA4 IDMA4 DONE I O DMADONE4 IDMA done RTC PD12 PD12 O RTC_WDI Watchdog signal to RTC PC5 PC5 I RTC_IRQ IRQ from RTC Auxiliary LEDs PC24 PC...

Страница 89: ...VSBC 6862 Rev 1 43 88 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Страница 90: ...This base address can be modified later using the ISB bits in the IMMR register This step is described below The third step is to configure the VSBC 6862 specific registers for purposes like memory co...

Страница 91: ...LBPC 00 Local bus pins as local bus 22 23 APPC 10 Pin mux BNKSEL 24 25 CS10PC 00 Pin mux CS10 26 Reserved 0 27 Reserved 0 28 31 MODCK_H 0101 Clock configuration bus 66 CPM 133 core 133 or 200 Then th...

Страница 92: ...delay 0 4 L2C 0 Secondary cache no 5 7 L2D 00 L2 cache hit delay 0 8 PLDP 0 Pipeline max depth 0 9 EAV 0 Enable address visibility no 10 11 Reserved 00 12 ETM 0 Extended transfer mode disabled 13 LET...

Страница 93: ...rs request no mask 18 LBPSE 0 Local bus parity byte select disabled 19 31 Reserved 0000000000000 Typical value SIUMCR 42200000 System Protection Control Register SYPCR This register controls the syste...

Страница 94: ...rv3_OUT 0 0 0 0 PA13 Rsrv4_MOD 0 1 0 0 PA14 FCC1_MII_RXD3 1 0 0 0 PA15 FCC1_MII_RXD2 1 0 0 0 PA16 FCC1_MII_RXD1 1 0 0 0 PA17 FCC1_MII_RXD0 1 0 0 0 PA18 FCC1_MII_TXD0 1 1 0 0 PA19 FCC1_MII_TXD1 1 1 0 0...

Страница 95: ...C PC0 IDMA1_DREQ 1 0 0 0 PC1 IDMA2_DREQ 1 0 1 0 PC2 IDMA2_DONE 1 0 1 1 PC3 IDMA2_DACK 1 1 0 1 PC4 FCC2_IRQ2 0 0 0 0 PC5 RTC_IRQ 0 0 0 0 PC6 FCC1_IRQ1 0 0 0 0 PC7 not used 0 1 0 0 PC8 SCC4_CD 1 0 0 0 P...

Страница 96: ...1 0 0 PD19 not used 0 1 0 0 PD20 SCC4_RTS 1 1 0 0 PD21 SCC4_TXD 1 1 0 0 PD22 SCC4_RXD 1 0 0 0 PD23 SCC3_RTS 1 1 0 0 PD24 not used 0 1 0 0 PD25 not used 0 1 0 0 PD26 SCC2_RTS 1 1 0 0 PD27 not used 0 1...

Страница 97: ...r Fixed length options without data consist of only a tag octet Only options 0 and 255 are fixed length All other options are variable length with a length octet following the tag octet The value of t...

Страница 98: ...52 and its length is 4 E g 34 04 00 12 E3 00 EPROM Option optional This option specifies the EPROM configuration binary code The code for this option is 56 and its length is 4 E g 38 04 04 2E 51 0F Fl...

Страница 99: ...ses below 0100 are reserved for the PowerQUICC II reset configuration By default the VSBC 6862 is provided with one Flash memory bank factory loaded with the ECMon debugger Detailed information can be...

Страница 100: ...egisters permit to configure general purposes for IP slot x D8 D9 D10 D11 D12 D13 D14 D15 Value x x x x x PF5V ENIRQ x Default x x x x x 0 0 x With ENIRQ Enable IRQ 0 Interrupt from IP to processor ar...

Страница 101: ...the DMA access for IP slot x D8 D9 D10 D11 D12 D13 D14 D15 Value x x x x x x ENDMA DMASRC Default x x x x x x 0 0 With ENDMA Enable DMA 0 DMA for IP x is disabled 1 DMA for IP x is enabled DMASRC DMA...

Страница 102: ...t Vector Register D RO CS4 781 These registers permit to acknowledge the IRQ for IP slot x D8 D9 D10 D11 D12 D13 D14 D15 Value V7 V6 V5 V4 V3 V2 V1 V0 Default 0 0 0 0 0 0 0 0 With V 7 0 This 8 bit val...

Страница 103: ...are Reset on board Writing this register with the value A resets the VME interrupter The VME interrupt is deactivated Writing this register with the value C generates a Power On Reset on board All res...

Страница 104: ...memory datasheet Local_rmw Local Read Modify Write cycle on shared memory 0 Normal operation the Flash RTC and SRAM are shared 1 Local exclusive access the Flash RTC and SRAM are accessible only by t...

Страница 105: ...e RW CS4 1053 This register permits to select the arbiter mode when board is in Slot1 mode D8 D9 D10 D11 D12 D13 D14 D15 Value VAM1 VAM0 x x x x x x Default 0 1 x x x x x x With VAM1 VAM0 Arbiter Mode...

Страница 106: ...AMA VME Master AM for window A RW CS4 105b VMAMB VME Master AM for window B RW CS4 105d These registers permit to complement the Address Modifiers AM for VME accesses and define the Data mode for VME...

Страница 107: ...s register always indicates the current VME IRQ Level even masked interrupts VHM VME interrupt Handler Mask RW CS4 1063 This register is used to mask incoming interrupt requests coming from VME bus D8...

Страница 108: ...is not masked Reading this register when no IRQ is pending is not allowed VINTER VME Interrupter command register WO CS4 1067 This register generates the corresponding VME IRQ 8260 D8 D9 D10 D11 D12...

Страница 109: ...evel acknowledged coded on 3 bits Warning This register is accessible from both VME bus and local processor The user must choose that this register is accessed by either VME either local processor but...

Страница 110: ...Activation of the Mailbox function 0 An access to the Mailbox did not generates an IRQ 1 An access to the Mailbox generates an local IRQ VME_rmw Activation of the pseudo RMW cycles 0 normal VME acces...

Страница 111: ...ddress for SRAM memory FLA18 FLA22 corresponding high order local addresses for Flash memory Warning This register is accessible from both VME bus and local processor The user must choose that this re...

Страница 112: ...erating Temperature 0 C to 70 C forced air cooling exit air Altitude 5 000 m Humidity NC 10 to 80 Vibration 2 Gs RMS 20 2000 Hz Random Non Operating Temperature 40 C to 100 C Altitude 15 000 m Humidit...

Страница 113: ...of cycles FLASH Read cycle single beat TBD SDRAM Read cycle single beat TBD Write cycle single beat TBD Read cycle burst 4 transfers TBD Write cycle burst 4 transfers TBD IP module 8 MHz mode memory...

Страница 114: ...ev 1 43 User s Guide 113 9 Physical board definition 9 1 PCB dimensions 1 7mm 160mm Figure 22 PCB dimensions Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Страница 115: ...VSBC 6862 Rev 1 43 114 9 2 Front panel Figure 23 Front panel Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Страница 116: ...re loaded monitor in Flash memory This monitor is a courtesy from ECRIN Automatismes and this free version will not be supported by ECRIN Automatismes An extended version is also available at ECRIN Au...

Страница 117: ...n be added or modified after releasing this manual and can be found and explained with the on line ECMon s help menu env Function Create modify or remove environment variable Syntax env name value Opt...

Страница 118: ...data items to copy destination starting destination address mcb uses a byte value mcw uses a short value mcl uses a long value mdb mdw mdl Function Displays the contents of memory byte value Syntax m...

Страница 119: ...ter PHY register value value of PHY register nload Function Load binary from TFTP server Syntax nload device offset filename host client gateway netmask Options device Ethernet device 0 for port 1 10...

Страница 120: ...Function Display the Vital Product Data Syntax vpd 10 2 2 Advanced information Preliminary information This chapter will describe the resources used for the monitor If the user will use ECMon with his...

Страница 121: ...he board to boot on the new software In case of problem the user can come back in the previous state inverting again the BootBnk jumper and resetting the board If the Window s Hyperterminal is used to...

Страница 122: ...er 5V 10V 0 10V 140 KSample sec burst mode level monitoring watchdog ADC 16 16 channels 12 bit Analog Digital Converter 5V 10V 0 10V programmable amplifier x1 x10 x100 140 KSample sec DAC 08B 8 channe...

Страница 123: ...38 4 KBaud 8 Bytes Rx FIFO 4 Bytes Tx FIFO Z85230 enhanced controller include TxClk RxClk signals SCC 04B Quad RS422 and RS485 Serial Interface Sync up to 2 MBaud Async up to 38 4 KBaud 8 Bytes Rx FI...

Страница 124: ...DAC I O connectors included IO 50 Universal Transition Module with terminal block for 50 singles wires for all I O IP modules I O connectors included SC 08D Octal RJ 45 8 pin connector with terminati...

Страница 125: ...VSBC 6862 Rev 1 43 124 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Страница 126: ...beforehand VSBC 6862 serial number Model name and number of PC Card and IP module OS version such as OS 9 pSOS VxWorks etc Software driver and application revisions Date of purchase and name of your d...

Страница 127: ...VSBC 6862 Rev 1 43 126 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Страница 128: ...cables four multi protocol serial cables CAB RJ45 DB9 Adaptor cable with RJ 45 and DB 9 female in RS 232 DTE mode CAB V6862 SCC 01 Adaptor cable with DB 15 high density male and DB 25 male in RS 232...

Страница 129: ...VSBC 6862 Rev 1 43 128 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Страница 130: ...dent d The board was installed improperly e The serial number of the board is defaced or missing ACTIS Computer will not under circumstances be liable for direct special or consequential damages such...

Страница 131: ...VSBC 6862 Rev 1 43 130 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Страница 132: ...ther VME boards and transition modules In this configuration the VSBC 6862 is VME master and can also be configured in system controller mode to arbiter the bus access for other masters Figure 24 Appl...

Страница 133: ...s two Fast Ethernet ports can access other boards without usage of the VME bus using a Fast Ethernet port to controls the specific peripherals of the SBC 6860 its second Fast Ethernet port can be used...

Страница 134: ...al ports For more convenience we added four SC 08DB transition modules to have standard DB 25 connections on front panel This single board system provides 32 synchronous or asynchronous serial ports f...

Страница 135: ...VSBC 6862 Rev 1 43 134 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Страница 136: ...30 overview 19 software description 80 Interrupt sources 82 IP modules ACTIS 121 connector for logic interface 38 I O connector 39 I O connector on VME 36 overview 14 software description 54 JTAG conn...

Страница 137: ...are description 48 SMC connector 1 29 connector 2 30 overview 17 software description 75 SRAM overview 14 software description 51 Termination resistors 18 VME connector P1 35 connector P2 36 overview...

Страница 138: ...service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE IN...

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