Actis VSBC-6862, Руководство пользователя

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VSBC-6862 Rev 1.43
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4.6. IP modules
The VSBC-6862 board provides four IP module slots, which are compliant with the ANSI/VITA 4-1995,
except the clock timing. (see the following Warning) It provides support for 8 MHz type and DMA
modules.
The IP interface offers a flexible architecture for I/O extension through inexpensive mezzanine
modules for different applications like:
•
Digital and analog functions
•
Serial communication controllers
•
Network and fieldbus interfaces
•
Graphic display
•
Transducer conditioning
•
Etc...
These interfaces give the possibility to easily customize the VSBC-6862.
This IP bus is implemented on the VSBC-6862 through a specific CPLD, which provides the interface
between the PowerQUICC II processor and the four IP module slots.
Warning
To avoid internal resynchronizations, the IP clock has been defined as derived from
the bus clock (66MHz). This permits the logic to be more efficient in terms of speed.
Thus, the IP clock is not VITA-4 compliant, the 8MHz is in fact 8.333 MHz.
This configuration has been successfully tested with our IP modules. However, this
can cause problems with some IP modules that use the IP clock to synchronize with
other boards.
Two solutions are possible:
1) Select another clock source on the IP clock (if possible)
2) Request a clock modification to ACTIS Computer. The bus clock will be
replaced by a 64MHz clock. The IP clock are correct, but the board will run
at 128MHz instead of 133MHz or 192MHz instead of 200MHz.
Some ratios for communication port can also be adjusted
A choice of IP modules and transition modules from ACTIS Computer is
available on our web site:
www.actis-computer.com
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