User's guide
13
Pattern matches
Pattern match
input(s)
ACKIN
Counter
input
INT
TdPM
TdACK
TdC
TwPM
Symbol
Parameters
Min
Max
Unit
TwPM
Pattern match input valid
(bit port)
750
ns
TdPM
Pattern match to INT delay
(bit port)
1.3
µs
TdACK
ACKIN to INT delay
(port with handshake)
3.1
µs
TdC
Counter input to INT delay
(timer mode)
1.2
µs
5.6. Z8536 registers access
Two cycles are necessary to address an internal register, as the internal CIO registers
are accessed through an internal pointer register.
The first cycle is the write pointer operation, into the control register (CR0 and CR1, on
CIO-32) which selects the internal register. The next cycle is the data access
operation.
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