CIO-32
14
The following state machine shows the internal register operation.
data
access
reset
state
WR
RD
RD or WR
software reset (D0 = 1)
write
pointer
state 0
state 1
hardware or
software reset
WR
D0 = 0
initialisation
RD or WR
D0 = 1
The CIO is on the reset state, after hardware or software reset. The software reset is
accomplished by writing D0=1 in CR0 or CR1 registers of the CIO-32. On the CIO-32
IP, the hardware reset is accomplished when the reset signal is asserted on the IP
logic interface. To leave this state, an initialization cycle is necessary: write D0=0 in
the control register, otherwise during a read cycle the CIO device returns always
D0=1. The state 0 waits for the pointer writing (in the control register) for the internal
register selection. After the data access (read or write cycle), the state machine
returns to the state 0, waiting for the next pointer writing.
A
minimum time of 500 ns
is required between the pointer writing and the data
access operation.
Pointer
Data
Write
500 ns min.
Data access
All internal CIO registers, including the internal data register, are accessed through
this method. The pointer register is automatically cleared after each following read or
write cycle.
A direct register access, without pointer writing cycle, is available for the data register
with the PADR to PDDR registers (see I/O space section).
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