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Flash*Freeze Mode

IGLOO PLUS Starter Kit User’s Guide

33

IGLOO PLUS I/O State in Flash*Freeze Mode

In IGLOO PLUS devices, users have multiple options in how to configure I/Os during Flash*Freeze 

mode:

1.

Hold the previous state.

2.

Set I/O pad to weak pull-up or pull-down.

3.

Tristate I/O pads.

The I/O configuration must be configured by the user in the I/O Attribute Editor or in a PDC constraint file, and can 
be done on a pin-by-pin basis. The output hold feature will hold the output in the last registered state, using the I/O pad 
weak pull-up or pull-down resistor when the FF pin is asserted. When inputs are configured with the hold feature 
enabled, the FPGA core side of the input will hold the last valid state of the input pad before the device entered 
Flash*Freeze mode. The input pad can be driven to any value, configured as tristate, or configured with the weak pull-up 
or pull-down I/O pad feature during Flash*Freeze mode, without affecting the hold state. If the weak pull-up or 
pull-down feature is used without the output hold feature, the input and output pads will maintain the configured weak 
pull-up or pull-down status during Flash*Freeze mode and normal operation. If a fixed weak pull-up or pull-down is 
defined on an output buffer or as bidirectional in output mode, and a hold state is also defined for the same pin, the pin 
will be configured in hold state mode during Flash*Freeze mode. During normal operation, the pin will be configured 
with the predefined weak pull-up or pull-down. Any I/Os that do not use the hold state or I/O pad weak pull-up or 
pull-down features will be tristated during Flash*Freeze mode and the FPGA core will be driven high by inputs. Inputs 
that are tristated during Flash*Freeze mode may be left floating without any reliability concern or impact to power 
consumption.

Table 4-2

 

shows the I/O pad state based on the configuration and buffer type.

Table 4-1 · Flash*Freeze Mode Type 1 and Type 2 – Signal Assertion and Deassertion Values

Signal

Assertion Value

Deassertion Value

Flash*Freeze (FF) pin

Low

High

LSICC signal

High

Low

Notes:

1. The Flash*Freeze (FF) pin is an active-Low signal, and LSICC is an active-High signal.

2. The LSICC signal is used only in Flash*Freeze mode type 2.

Table 4-2 · IGLOO PLUS Flash*Freeze Mode (type 1 and type 2)—I/O Pad State 

Buffer Type

Hold State

I/O Pad 

Weak Pull-Up/-Down

I/O Pad State in 

Flash*Freeze Mode

Input

Enabled

Enabled

Weak pull-up/pull-down

1

Disabled

Enabled

Weak pull-up/pull-down

2

Enabled

Disabled

Tristate

1

Disabled

Disabled

Tristate

2

Notes:

1. Internal core logic driven by this input buffer will be set to the value this I/O had when entering Flash*Freeze mode.

2. Internal core logic driven by this input buffer will be tied High as long as the device is in Flash*Freeze mode.

3. For bidirectional buffers: Internal core logic driven by the input portion of the bidirectional buffer will be set to the hold state.

Downloaded from 

Elcodis.com

 

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Содержание IGLOO PLUS Starter Kit

Страница 1: ...IGLOO PLUS Starter Kit User s Guide Downloaded from Elcodis com electronic components distributor...

Страница 2: ...Information in this document is subject to change without notice Actel assumes no responsibility for any errors that may appear in this document This document contains confidential proprietary informa...

Страница 3: ...Power Modes 24 Battery 25 Potentiometer and Voltage Sweep 25 Current Measurement 26 4 Operation of Board Components 29 Clock Oscillator 29 Reset 29 Flash Freeze Mode 30 Push Button Switches 37 DIP Sw...

Страница 4: ...Guide B Product Support 57 Customer Service 57 Actel Customer Technical Support Center 57 Actel Technical Support 57 Website 57 Contacting the Customer Technical Support Center 57 Index 59 Downloaded...

Страница 5: ...strates the ultra low power of Actel IGLOO PLUS devices Table 1 lists the contents of the box Figure 1 IGLOO PLUS Starter Kit Board Table 1 IGLOO PLUS Starter Kit Contents Quantity Contents 1 IGLOO PL...

Страница 6: ...Downloaded from Elcodis com electronic components distributor...

Страница 7: ...n your design In addition the Libero Integrated Design Environment IDE tool suite now includes power driven layout PDL which can reduce the power consumption of designs up to 30 percent The evaluation...

Страница 8: ...ctel website on the IGLOO PLUS Starter Kit page http www actel com products hardware devkits_boards iglooplus_starter aspx To view the PCB design layout files you can use the Allegro Free Physical Vie...

Страница 9: ...IGLOO PLUS Board Stackup IGLOO PLUS Starter Kit User s Guide 9 Figure 1 2 IGLOO PLUS Top Silkscreen L1 Downloaded from Elcodis com electronic components distributor...

Страница 10: ...Board Components and Settings 10 IGLOO PLUS Starter Kit User s Guide Figure 1 3 IGLOO PLUS Bottom Silkscreen L10 Downloaded from Elcodis com electronic components distributor...

Страница 11: ...e jumper to disconnect external battery source J8 Pin 2 3 Remove jumper to disconnect VCCI_1 power J9 Pin 1 4 Select WALL BAT VUSB for 5V_SOURCE Pin 1 4 VUSB Pin 2 4 BAT Pin 3 4 WALL J10 5 V Brick J11...

Страница 12: ...1 2 Remove each jumper to disconnect any of the 2 FET Switches 1 2 from FPGA J23 3V3_SWITCH1 J24 3V3_SWITCH2 J25 J27 Pin 1 2 Remove each jumper to disconnect any of the 3 FET LEDs from FPGA J25 FET_P1...

Страница 13: ...5 J45 LED6 J44 LED7 J43 LED8 Table 1 2 Switch Settings Switch Default Setting Comment SW1 SW4 Push button switches for SWITCH 1 4 SW5 CLOSE Contains DIP switches for 3V3_SWITCH 1 2 DSW5 CLOSE Contains...

Страница 14: ...Downloaded from Elcodis com electronic components distributor...

Страница 15: ...rogrammable flash technology In system programming ISP and security High performance routing hierarchy Advanced I O Selectable Schmitt trigger inputs Clock conditioning circuit CCC and PLL Embedded me...

Страница 16: ...CC3 J7 VCC4 J11 VCOMPLF H1 VCCPLF J1 GND1 A4 GND2 A9 GND3 A14 GND4 B2 GND5 B17 GND6 C10 GND7 C15 GND8 D3 GND9 D8 GND10 D13 GND11 F14 GND12 G2 GND13 G7 GND14 G8 GND15 G10 GND16 G11 GND17 G17 GND18 H7 G...

Страница 17: ...34RSB0 D9 IO35RSB0 A10 IO36RSB0 E10 IO37RSB0 B10 IO56RSB0 E12 IO55RSB0 D12 IO54RSB0 A16 IO53RSB0 F12 IO52RSB0 C14 IO51RSB0 F11 IO50RSB0 C13 IO49RSB0 B15 IO48RSB0 A15 IO47RSB0 D11 IO46RSB0 B14 IO45RSB0...

Страница 18: ...6 TP TP16 TP TP26 TP TP26 TP TP210 T TP210 T TP183 T TP183 T TP30 TP TP30 TP TP42 TP TP42 TP TP226 T TP226 T TP208 T TP208 T TP17 TP TP17 TP TP48 TP TP48 TP TP142 T TP142 T TP25 TP TP25 TP TP45 TP TP4...

Страница 19: ...TP TP130 TP TP130 TP TP126 TP TP126 TP TP141 TP TP141 TP TP127 TP TP127 TP TP163 TP TP163 TP IO108RSB2 P14 IO109RSB2 N14 IO110RSB2 R15 IO111RSB2 N12 IO112RSB2 P12 IO113RSB2 M12 IO114RSB2 R14 IO115RSB...

Страница 20: ...O175RSB3 K5 IO176RSB3 M3 IO177RSB3 K6 IO178RSB3 N2 IO179RSB3 K4 IO180RSB3 N1 IO181RSB3 J6 IO182RSB3 L3 IO183RSB3 J5 IO184RSB3 M1 IO185RSB3 J4 IO195RSB3 H3 IO196RSB3 F2 IO197RSB3 H4 IO198RSB3 G3 IO199R...

Страница 21: ...ower supply in a separate I O bank gives greater flexibility in supply selection and simplifies power supply and PCB design If the JTAG interface is neither used or planned for use the VJTAG pin toget...

Страница 22: ...01uF C51 0 01uF C51 0 01uF C48 0 1uF C48 0 1uF C58 0 01uF C58 0 01uF C30 0 1uF C30 0 1uF C44 0 01uF C44 0 01uF C49 0 01uF C49 0 01uF C52 0 01uF C52 0 01uF C54 10uF 16V C54 10uF 16V C31 10uF 16V C31 10...

Страница 23: ...V 2 5 V and 1 5 V The regulator can be switched between the 1 5 V and 1 2 V rail because the FPGA core functions at 1 2 V but is programmed at 1 5 V Figure 3 1 USB Active Inrush Limiter Table 3 1 Pow...

Страница 24: ...a summary of the power modes available with IGLOO PLUS devices in general and is extracted from the Actel s Flash Freeze Technology and Low Power Modes chapter of the IGLOO PLUS FPGA Fabric User s Gui...

Страница 25: ...e Sweep A potentiometer is located on the left hand side of the board to provide the voltage sweep function to sweep VCC Figure 3 3 One primary function of the potentiometer is to show battery operati...

Страница 26: ...re separated and two of the banks have an option to power up though a 3 3 V or 2 5 V source as shown in Figure 3 7 on page 28 Voltage sources can be selected using jumpers or can be selected to sweep...

Страница 27: ...27 Figure 3 6 Current Measurement Headers for Power Rails VCCI_0 VCCI_1 VCCI_2 VCCI_3 VCC VJTAG VPUMP Current Measurement IGLOO PLUS 3 3 V 3 3 V 3 3 V 1 5 V 3 3 V or 2 5 V 3 3 V or 2 5 V 3 3 V Downlo...

Страница 28: ...P VCC_SWEEP VCC_SWEEP 1 2 3 4 J12 HDR_4PIN J12 HDR_4PIN 1 2 3 4 J8 HDR_4PIN J8 HDR_4PIN 1 2 3 J18 HDR_3PIN J18 HDR_3PIN 1 2 3 J14 HDR_3PIN J14 HDR_3PIN 1 2 3 4 J16 4PIN_HEADER J16 4PIN_HEADER 1 2 3 J1...

Страница 29: ...illator Schematic Reset An RC type push button reset switch to the FPGA is provided on board The Schmitt Trigger chip U13 however is NOT populated An on board Schmitt Trigger chip is not required beca...

Страница 30: ...Flash Freeze mode In Flash Freeze type 1 entering and exiting the mode is exclusively controlled by the assertion and deassertion of the FF pin This enables an external processor or human interface de...

Страница 31: ...h In this mode FF pin assertion or deassertion is the only condition that determines entering or exiting Flash Freeze mode Figure 4 4 An INBUF_FF I O buffer macro must be used to identify the Flash Fr...

Страница 32: ...nt to enter Flash Freeze mode type 2 both the FF pin and LSICC signal must be asserted Figure 4 7 shows the timing diagram for entering and exiting Flash Freeze mode type 2 After exiting Flash Freeze...

Страница 33: ...ring Flash Freeze mode During normal operation the pin will be configured with the predefined weak pull up or pull down Any I Os that do not use the hold state or I O pad weak pull up or pull down fea...

Страница 34: ...gn which provides additional details on demonstrating these Flash Freeze variants IGLOO PLUS Board Demo on page 51 Output Enabled Don t care Weak pull to hold state Disabled Enabled Weak pull up pull...

Страница 35: ...o the demo design that demonstrates the Flash Freeze variants with these switches Figure 4 9 Two I Os Controlled via DIP Switch Toggling High or Low 3V3_SWITCH2 4 3V3_SWITCH1 4 3V3_SWITCH1 4 3V3_SWITC...

Страница 36: ...h will help demonstrate the Flash Freeze variants Figure 4 10 FET LEDs for Debugging V3P3 V3P3 V3P3 FET_N 4 FET_P1 4 FET_P2 P TYPE FET N TYPE FET D13 LO T67K L1M2 24 Z D13 LO T67K L1M2 24 Z 1 2 3 G S...

Страница 37: ...CH1 4 SWITCH2 4 SWITCH3 4 SWITCH4 4 SWITCH3 4 SWITCH4 4 Mfr P N KSC403J 50SH LFG Mfr ITT INDUSTRIES Mfr P N KSC403J 50SH LFG Mfr ITT INDUSTRIES Mfr P N KSC403J 50SH LFG Mfr ITT INDUSTRIES Mfr P N KSC4...

Страница 38: ..._SWITCH5 4 D_SWITCH6 4 D_SWITCH7 4 D_SWITCH8 4 R54 4 7K R54 4 7K R56 4 7K R56 4 7K R53 4 7K R53 4 7K R57 4 7K R57 4 7K R55 4 7K R55 4 7K R60 4 7K R60 4 7K R58 4 7K R58 4 7K 1 2 3 4 5 6 7 8 16 15 14 13...

Страница 39: ...LO T67K L1M2 24 Z D4 LO T67K L1M2 24 Z D4 LO T67K L1M2 24 Z R29 1 5K R29 1 5K D7 LO T67K L1M2 24 Z D7 LO T67K L1M2 24 Z R31 1 5K R31 1 5K R30 1 5K R30 1 5K D6 LO T67K L1M2 24 Z D6 LO T67K L1M2 24 Z R2...

Страница 40: ...TP TP293 TP TP276 TP TP276 TP TP61 TP TP61 TP TP267 TP TP267 TP TP304 TP TP304 TP TP311 TP TP311 TP TP270 TP TP270 TP TP55 TP TP55 TP TP261 TP TP261 TP TP280 TP TP280 TP TP192 TP TP192 TP TP281 TP TP...

Страница 41: ...he IGLOO PLUS Starter Kit website page http www actel com products hardware devkits_boards iglooplus_starter aspx Figure 4 19 OLED Display Schematic VP_10V V3P3 V3P3 PACER_D0 4 PACER_RES 4 PACER_D2 4...

Страница 42: ...provided on these signal lines Figure 4 20 Interface Connector Schematic VUSB V3P3 GPIOA_29 3 GPIOA_33 3 GPIOA_31 3 GPIOA_35 3 GPIOA_34 3 GPIOA_36 3 GPIOA_26 3 GPIOA_28 3 GPIOA_30 3 GPIOA_32 3 GPIOA_...

Страница 43: ...tings selected you can use the HyperTerminal program to communicate with a design running in the IGLOO PLUS FPGA device Information on the USB to UART bridge datasheet and device drivers are available...

Страница 44: ...Kit website page http www actel com products hardware devkits_boards iglooplus_starter aspx Figure 4 22 SPI Flash Schematics Note Either the Winbond or Atmel SPI flash will be populated on the board...

Страница 45: ...socket is designed to interface to the 12 pin right angle male header on the IGLOO PLUS kit One of the pins is a special VJTAGENB signal that goes high when programming is taking place and returns to...

Страница 46: ...VJTAGENB 3 TCK 5 VPUMP 5 TRST 5 TDI 5 TMS 5 VJTAG 5 TDO 5 Programmer Mfr P N TSW 106 08 T D RA Mfr SAMTEC 6X2 Right Angled Header TCK 2 GND3 4 TDI 6 TRSTB 8 VPUMP 10 VJTAGENB 1 TMS 3 GND2 5 VJTAG 7 TD...

Страница 47: ...built on a four layer PCB with the layers arranged in the following stackup 1 Top signal layer Figure 4 2 Ground plane 3 Power plane 4 Bottom signal layer Figure 4 26 on page 48 Figure 4 25 Low Cost...

Страница 48: ...Operation of Board Components 48 IGLOO PLUS Starter Kit User s Guide Figure 4 26 Low Cost Programming Stick Bottom Silkscreen Downloaded from Elcodis com electronic components distributor...

Страница 49: ...o other power source power brick is attached to the IGLOO PLUS board 4 When using the FlashPro software the programmer to select is the FlashPro3 The LCPS is functionally equivalent to a FlashPro prog...

Страница 50: ...Downloaded from Elcodis com electronic components distributor...

Страница 51: ...and no external power supply is required A 5 V wall jack connector could be used when USB cable is not available The board does not switch seamlessly between the power brick and USB so the power sour...

Страница 52: ...lue prior to entering Flash Freeze mode 3 To measure power of the FPGA core during and after Flash Freeze mode simply remove jumper J12 and use a multimeter capable of reading A current across J12 Dem...

Страница 53: ...D D14 is ON due to the pull down resister configuration N Type FET LED D15 turns ON due to the pull up resister configuration Toggle the FET Switches back and forth Observe that the LEDs are unaffecte...

Страница 54: ...presents the LED state during Flash Freeze mode Table 6 4 FET Truth Table Input Output FET Switch 1 FET Switch 2 P Type FET LED D13 active low HOLD P Type FET LED D14 active low Pull down N Type FET L...

Страница 55: ...IGLOO PLUS Overview http www actel com products iglooplus default aspx IGLOO PLUS Datasheet http www actel com documents IGLOOPLUS_DS pdf IGLOO PLUS FPGA Fabric User s Guide http www actel com docume...

Страница 56: ...Downloaded from Elcodis com electronic components distributor...

Страница 57: ...re software and design questions The Customer Technical Support Center spends a great deal of time creating application notes and answers to FAQs So before you contact us please visit our online resou...

Страница 58: ...ur question and then issues a case number The Center then forwards the information to a queue where the first available application engineer receives the data and returns your call The phone hours are...

Страница 59: ...switch 34 H hardware components 7 I I O test pins 40 IGLOO PLUS Starter Kit board photograph 5 J jumper settings 11 jumpers settings 11 L LCPS 45 bottom silkscreen 48 stackup 47 top silkscreen 47 LED...

Страница 60: ...0 IGLOO PLUS Starter Kit User s Guide Index submit case online 57 U USB to UART interface 43 User LEDs 39 W web based technical support 57 Downloaded from Elcodis com electronic components distributor...

Страница 61: ...Downloaded from Elcodis com electronic components distributor...

Страница 62: ...0 Actel Japan EXOS Ebisu Building 4F 1 24 14 Ebisu Shibuya ku Tokyo 150 Japan Phone 81 03 3445 7671 Fax 81 03 3445 7668 www jp actel com Actel Hong Kong Room 2107 China Resources Building 26 Harbour R...

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