Actel IGLOO PLUS Starter Kit, Руководство пользователя, Страница: 29 / 62

IGLOO PLUS Starter Kit User’s Guide 29
4
Operation of Board Components
This chapter describes operation of the IGLOO PLUS evaluation board.
Clock Oscillator
One 20 MHz clock oscillator with 50 PPM is provided on the board. This clock oscillator is connected to the FPGA to
provide a system or reference clock. The PLL can be configured and instantiated in the FPGA to generate a wide range
of clock frequencies.
Reference
For more information, refer to the IGLOO PLUS Starter Kit website page:
http://www.actel.com/products/hardware/devkits_boards/iglooplus_starter.aspx .
Schematic
Figure 4-1 shows the schematic for the clock oscillator.
Figure 4-1 · Clock Oscillator Schematic
Reset
An RC type push-button reset switch to the FPGA is provided on-board. The Schmitt Trigger chip (U13), however, is
NOT populated. An on-board Schmitt Trigger chip is not required because Schmitt Trigger is one of the many
advanced I/O features of the IGLOO PLUS FPGA family. To improve noise immunity, ensure that the Schmitt Trigger
option for this reset input pin is enabled in the FPGA design. If the IGLOO PLUS FPGA is swapped out with a device
that does not have the advance Schmitt Trigger I/O feature, the Schmitt Trigger chip (U13) should be populated.
V3P3
OSC_CLK [4]
R43
10K R43
10K
R64
22
R64
22
C39
0.1uF
C39
0.1uF
OUT_EN
1
GND
2
OUTPUT
3
VDD
4
U10
OSCILLATOR
Mfg P/N = SIT8002AC-43-33E
Manufacturer = SI TIME
U10
OSCILLATOR
Mfg P/N = SIT8002AC-43-33E
Manufacturer = SI TIME
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