SERIES PMC408 PCI MEZZANINE CARD 32-CHANNEL DIGITAL I/O MODULE
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accomplishing “loopback” control of the output. A “0” bit means that
the corresponding input signal is below the threshold value (or the
tandem output mosfet is ON), a “1” bit means that the corresponding
input signal is at or above the threshold value (or the tandem mosfet
is OFF and pulled up).
Thirty-two possible input channels numbered 0 through 31 may
be read. Channel read operations use 8-bit (LSB or MSB), or 16-bit
data transfers with the lower ordered bits corresponding to the lower-
numbered channels for the register of interest (see below). Register
A monitors input channels 0 through 15. Register B monitors input
channels 16 through 31.
It is recommended that unused inputs not be left floating, but
pulled low by turning on the corresponding tandem output (see PMC
Digital Output Registers).
REGISTER A (INPUT CHANNELS 0 THROUGH 15):
MSB _ _ _ _ _ _ _ _ _ _ _ _ _ _ LSB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH15.....................................CH8 CH7....................................CH0
REGISTER B (INPUT CHANNELS 16 THROUGH 31):
MSB _ _ _ _ _ _ _ _ _ _ _ _ _ _ LSB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH31..................................CH24 CH23.................................CH16
Digital Output Registers A & B (Read/Write)
When the Digital Output Channel Data Registers are written to,
the value written is represented at the corresponding output
channels. A “0” bit means that the corresponding output switch is
OPEN (OFF). Writing a “1” bit CLOSES the corresponding output
switch (turns it ON). There are two ways to accomplish an output
read. Reading the digital output channel register returns the state
configuration of this register (which is equivalent to the output
mosfet gate signal). Since input channels operate in tandem with
the output channels, reading the digital input channel register will
return the actual state of the output (it returns the level of the output
mosfet drain). That is, writing a ‘1’ to an output turns the switch ON
(gate signal high). In turn, this drives the drain low (mosfet is
conducting). As such, a read of the input channel register will be the
inverse of a read of the output channel register for a loaded output
channel.
Read/Write Control for 32 output channels numbered 0 through
31 is provided. Channel state Read/Write operations use 8-bit, 16-
bit, or 32-bit data transfers with the lower ordered bits corresponding
to the lower-numbered channels for the register of interest (see
below). Register A controls output channels 0 through 15. Register
B controls output channels 16 through 31.
REGISTER A (OUTPUT SWITCHES 0 THROUGH 15):
MSB _ _ _ _ _ _ _ _ _ _ _ _ _ _ LSB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH15...................................CH08 CH7....................................CH0
REGISTER B (OUTPUT SWITCHES 16 THROUGH 31):
MSB _ _ _ _ _ _ _ _ _ _ _ _ _ _ LSB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH31...................................CH24 CH23.................................CH16
Each output channel register can be conveniently read back for
verification purposes. However, for critical control applications, it is
recommended that outputs be directly fed back to input points and
the input points monitored (loopback I/O). By design, input channels
are tied to the drains of the tandem output mosfet and a read of the
input channel register will return the inverse of a read of the output
channel register (a read of the input returns the drain level, a read of
the output returns the gate level). This is an efficient method of
accomplishing loopback output control without requiring additional
channels. However, this only applies for a loaded drain (a pullup or
other load connected to the drain).
All outputs are OFF (switch OPEN) following a power-on reset,
and are immediately cleared following a system reset. It is
recommended that unused outputs be turned on so that the
corresponding unused inputs are pulled low, rather than floating.
Interrupt Enable Register (R/W)
The digital input channel Interrupt Enable Registers provide a
mask bit for each of the 8 possible interrupt channels (channels 0-7
only). A “0” bit will prevent the corresponding input channel from
generating an external interrupt. A “1” bit will allow the
corresponding input channel to generate an interrupt. The unused
upper 8 bits of these 16-bit registers are “Don’t Care” and will always
read high (1’s).
INTERRUPT ENABLE REGISTER:
MSB _ _ _ _ _ _ _ _ _ _ _ _ _ _ LSB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
X X X X X X X X CH7....................................CH0
All input channel interrupts are masked (“0”) following a reset.
Interrupt Type (COS or H/L) Configuration Register (R/W)
The Interrupt Type Configuration Registers determine the type
of input channel transition that will generate an interrupt for each of
the 8 possible interrupt channels (channels 0-7 only). A “0” bit
means that an interrupt will be generated when the input channel
level specified by the Interrupt Polarity Register occurs (i.e. Low or
High level transition interrupt). A “1” bit means the interrupt will
occur when a Change-Of-State (COS) occurs at the corresponding
input channel (i.e. any state transition). The unused upper 8 bits of
these 16-bit registers are “Don’t Care” and will always read high
(1’s). Note that interrupts will not occur unless they are enabled.
INTERRUPT TYPE (COS or H/L) CONFIGURATION REGISTER:
MSB _ _ _ _ _ _ _ _ _ _ _ _ _ _ LSB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
X X X X X X X X CH7....................................CH0
All bits are set to “0” following a reset which means that the
inputs will cause interrupts for the levels specified by the digital input
channel Interrupt Polarity Register.
Interrupt Polarity Register (R/W)
The Interrupt Polarity Register determines the level that will
cause a channel interrupt to occur for each of the 8 possible
interrupt channels (channels 0-7 only). A “0” bit specifies that an
interrupt will occur when the corresponding input channel is
BELOW
TTL threshold (i.e. a “0” in the digital input channel data register). A
“1” bit means that an interrupt will occur when the input channel is
ABOVE
TTL
threshold (i.e. a “1” in the digital input channel data
register). Note that no interrupts will occur unless they are enabled
by the Interrupt Enable Register. Further, the Interrupt Polarity
